; 80C152 MOD FILE ; REV. 1.3 OCTOBER 17, 1988 P0 DATA 080H ;PORT 0 SP DATA 081H ;STACK POINTER DPL DATA 082H ;DATA POINTER - LOW BYTE DPH DATA 083H ;DATA POINTER - HIGH BYTE GMOD DATA 084H ;GSC MODE TFIFO DATA 085H ;GSC TRANSMIT BUFFER PCON DATA 087H ;POWER CONTROL TCON DATA 088H ;TIMER CONTROL TMOD DATA 089H ;TIMER MODE TL0 DATA 08AH ;TIMER 0 - LOW BYTE TL1 DATA 08BH ;TIMER 1 - LOW BYTE TH0 DATA 08CH ;TIMER 0 - HIGH BYTE TH1 DATA 08DH ;TIMER 1 - HIGH BYTE P1 DATA 090H ;PORT 1 P5 DATA 091H ;PORT 5 DCON0 DATA 092H ;DMA CONTROL 0 DCON1 DATA 093H ;DMA CONTROL 1 BAUD DATA 094H ;GSC BAUD RATE ADR0 DATA 095H ;GSC MATCH ADDRESS 0 SCON DATA 098H ;LSC CONTROL SBUF DATA 099H ;LSC BUFFER P2 DATA 0A0H ;PORT 2 P6 DATA 0A1H ;PORT 6 SARL0 DATA 0A2H ;DMA CHANNEL 0 SOURCE ADDRESS - LO BYTE SARH0 DATA 0A3H ;DMA CHANNEL 0 SOURCE ADDRESS - HI BYTE IFS DATA 0A4H ;GSC INTERFRAME SPACE ADR1 DATA 0A5H ;GSC MATCH ADDRESS 1 IE DATA 0A8H ;INTERRUPT ENABLE REGISTER 0 P3 DATA 0B0H ;PORT 3 SARL1 DATA 0B2H ;DMA CHANNEL 1 SOURCE ADDRESS - LO BYTE SARH1 DATA 0B3H ;DMA CHANNEL 1 SOURCE ADDRESS - HI BYTE SLOTTM DATA 0B4H ;GSC SLOT TIME ADR2 DATA 0B5H ;GSC MATCH ADDRESS 2 IP DATA 0B8H ;INTERRUPT PRIORITY REGISTER 0 P4 DATA 0C0H ;PORT 4 DARL0 DATA 0C2H ;DMA CHANNEL 0 DESTINATION ADDRESS - LO BYTE DARH0 DATA 0C3H ;DMA CHANNEL 0 DESTINATION ADDRESS - HI BYTE BKOFF DATA 0C4H ;GSC BACKOFF TIMER ADR3 DATA 0C5H ;GSC MATCH ADDRESS 3 IEN1 DATA 0C8H ;INTERRUPT ENABLE REGISTER 1 PSW DATA 0D0H ;PROGRAM STATUS WORD DARL1 DATA 0D2H ;DMA CHANNEL 1 DESTINATION ADDRESS - LO BYTE DARH1 DATA 0D3H ;DMA CHANNEL 1 DESTINATION ADDRESS - HI BYTE TCDCNT DATA 0D4H ;GSC XMIT COLLISION COUNTER AMSK0 DATA 0D5H ;GSC ADDRESS MASK 0 TSTAT DATA 0D8H ;GSC TRANSMIT STATUS ACC DATA 0E0H ;ACCUMULATOR BCRL0 DATA 0E2H ;DMA BYTE COUNT 0 - LOW BYTE BCRH0 DATA 0E3H ;DMA BYTE COUNT 0 - HI BYTE PRBS DATA 0E4H ;GSC PSEUDO-RANDOM SEQUENCE AMSK1 DATA 0E5H ;GSC ADDRESS MASK 1 RSTAT DATA 0E8H ;GSC RECEIVE STATUS B DATA 0F0H ;MULTIPLICATION REGISTER BCRL1 DATA 0F2H ;DMA BYTE COUNT 1 - LOW BYTE BCRH1 DATA 0F3H ;DMA BYTE COUNT 1 - HI BYTE RFIFO DATA 0F4H ;GSC RECEIVE BUFFER MYSLOT DATA 0F5H ;GSC SLOT ADDRESS IPN1 DATA 0F8H ;INTERRUPT PRIORITY REGISTER 1 IT0 BIT 088H ;TCON.0 - EXT. INTERRUPT 0 TYPE IE0 BIT 089H ;TCON.1 - EXT. INTERRUPT 0 EDGE FLAG IT1 BIT 08AH ;TCON.2 - EXT. INTERRUPT 1 TYPE IE1 BIT 08BH ;TCON.3 - EXT. INTERRUPT 1 EDGE FLAG TR0 BIT 08CH ;TCON.4 - TIMER 0 ON/OFF CONTROL TF0 BIT 08DH ;TCON.5 - TIMER 0 OVERFLOW FLAG TR1 BIT 08EH ;TCON.6 - TIMER 1 ON/OFF CONTROL TF1 BIT 08FH ;TCON.7 - TIMER 1 OVERFLOW FLAG GRXD BIT 090H ;P1.0 - GSC RECEIVER DATA GTXD BIT 091H ;P1.1 - GSC TRANSMIT DATA DEN BIT 092H ;P1.2 - DRIVE ENABLE TXC BIT 093H ;P1.3 - GSC TRANSMIT CLOCK RXC BIT 094H ;P1.4 - GSC RECEIVE CLOCK HLD BIT 095H ;P1.5 - HOLD REQUEST HLDA BIT 096H ;P1.6 - HOLD ACKNOWLEDGE RI BIT 098H ;SCON.0 - RECEIVE INTERRUPT FLAG TI BIT 099H ;SCON.1 - TRANSMIT INTERRUPT FLAG RB8 BIT 09AH ;SCON.2 - RECEIVE BIT 8 TB8 BIT 09BH ;SCON.3 - TRANSMIT BIT 8 REN BIT 09CH ;SCON.4 - RECEIVE ENABLE SM2 BIT 09DH ;SCON.5 - SERIAL MODE CONTROL BIT 2 SM1 BIT 09EH ;SCON.6 - SERIAL MODE CONTROL BIT 1 SM0 BIT 09FH ;SCON.7 - SERIAL MODE CONTROL BIT 0 EX0 BIT 0A8H ;IE.0 - EXTERNAL INTERRUPT 0 ENABLE ET0 BIT 0A9H ;IE.1 - TIMER 0 INTERRUPT ENABLE EX1 BIT 0AAH ;IE.2 - EXTERNAL INTERRUPT 1 ENABLE ET1 BIT 0ABH ;IE.3 - TIMER 1 INTERRUPT ENABLE ES BIT 0ACH ;IE.4 - SERIAL PORT INTERRUPT ENABLE EA BIT 0AFH ;IE.7 - GLOBAL INTERRUPT ENABLE RXD BIT 0B0H ;P3.0 - SERIAL PORT RECEIVE INPUT TXD BIT 0B1H ;P3.1 - SERIAL PORT TRANSMIT OUTPUT INT0 BIT 0B2H ;P3.2 - EXTERNAL INTERRUPT 0 INPUT INT1 BIT 0B3H ;P3.3 - EXTERNAL INTERRUPT 1 INPUT T0 BIT 0B4H ;P3.4 - TIMER 0 COUNT INPUT T1 BIT 0B5H ;P3.5 - TIMER 1 COUNT INPUT WR BIT 0B6H ;P3.6 - WRITE CONTROL FOR EXT. MEMORY RD BIT 0B7H ;P3.7 - READ CONTROL FOR EXT. MEMORY PX0 BIT 0B8H ;IP.0 - EXTERNAL INTERRUPT 0 PRIORITY PT0 BIT 0B9H ;IP.1 - TIMER 0 PRIORITY PX1 BIT 0BAH ;IP.2 - EXTERNAL INTERRUPT 1 PRIORITY PT1 BIT 0BBH ;IP.3 - TIMER 1 PRIORITY PS BIT 0BCH ;IP.4 - SERIAL PORT PRIORITY EGSRV BIT 0C8H ;IEN1.0 - GSC RECEIVE VALID INTERRUPT ENABLE EGSRE BIT 0C9H ;IEN1.1 - GSC RECEIVE ERROR INTERRUPT ENABLE EDMA0 BIT 0CAH ;IEN1.2 - DMA CHANNEL 0 REQUEST INTERRUPT ENABLE EGSTV BIT 0CBH ;IEN1.3 - GSC TRANSMIT VALID INTERRUPT ENABLE EDMA1 BIT 0CCH ;IEN1.4 - DMA CHANNEL 1 REQUEST INTERRUPT ENABLE EGSTE BIT 0CDH ;IEN1.5 - GSC TRANSMIT ERROR INTERRUPT ENABLE P BIT 0D0H ;PSW.0 - ACCUMULATOR PARITY FLAG OV BIT 0D2H ;PSW.2 - OVERFLOW FLAG RS0 BIT 0D3H ;PSW.3 - REGISTER BANK SELECT 0 RS1 BIT 0D4H ;PSW.4 - REGISTER BANK SELECT 1 F0 BIT 0D5H ;PSW.5 - FLAG 0 AC BIT 0D6H ;PSW.6 - AUXILIARY CARRY FLAG CY BIT 0D7H ;PSW.7 - CARRY FLAG DMA BIT 0D8H ;TSTAT.0 - DMA SELECT TEN BIT 0D9H ;TSTAT.1 - TRANSMIT ENABLE TFNF BIT 0DAH ;TSTAT.2 - TRANSMIT FIFO NOT FULL TDN BIT 0DBH ;TSTAT.3 - TRANSMIT DONE TCDT BIT 0DCH ;TSTAT.4 - TRANSMIT COLLISION DETECT UR BIT 0DDH ;TSTAT.5 - UNDERRUN NOACK BIT 0DEH ;TSTAT.6 - NO ACKNOWLEDGE LNI BIT 0DFH ;TSTAT.7 - LINE IDLE HBAEN BIT 0E8H ;RSTAT.0 - HARDWARE BASED ACKNOWLEDGE ENABLE GREN BIT 0E9H ;RSTAT.1 - RECEIVER ENABLE RFNE BIT 0EAH ;RSTAT.2 - RECEIVE FIFO NO EMPTY RDN BIT 0EBH ;RSTAT.3 - RECEIVE DONE CRCE BIT 0ECH ;RSTAT.4 - CRC ERROR AE BIT 0EDH ;RSTAT.5 - ALIGNMENT ERROR RCABT BIT 0EEH ;RSTAT.6 - RECEIVER COLLISION/ABORT DETECT OVR BIT 0EFH ;RSTAT.7 - OVERRUN PGSRV BIT 0F8H ;IPN1.0 - GSC RECEIVE VALID PRIORITY PGSRE BIT 0F9H ;IPN1.1 - GSC RECEIVE ERROR PRIORITY PDMA0 BIT 0FAH ;IPN1.2 - DMA CHANNEL 0 REQUEST PRIORITY PGSTV BIT 0FBH ;IPN1.3 - GSC TRANSMIT VALID PRIORITY PDMA1 BIT 0FCH ;IPN1.4 - DMA CHANNEL 1 REQUEST PRIORITY PGSTE BIT 0FDH ;IPN1.5 - GSC TRANSMIT ERROR PRIORITY