Pinout of programmer adapter ADP-EPM7032

for ALTERA EPM-7032 in PLCC-44 package

(numbers in brackets are for the QFP-44 package)

DEVICE

DIP40

SIGNAL

 

SIGNAL

DIP40

DEVICE

1 (39)

17

NTPW

 

EDT/Vpp

22

44 (38)

2 (40)

21

MTIN

 

SK

[35]

43 (37)

3 (41)

30

Vcc

 

Vss

20

42 (36)

4 (42)

[29]

SCK

 

SDINB

10

41 (35)

5 (43)

9

SDINA

 

MT

31

40 (34)

6 (44)

25

reserved

 

A0

1

39 (33)

7 (1)

18

BE

 

A1

2

38 (32)

8 (2)

24

BEM

 

A2

3

37 (31)

9 (3)

26

reserved

 

A3

4

36 (30)

10 (4)

20

Vss

 

Vcc

30

35 (29)

11 (5)

27

reserved

 

A4

5

34 (28)

12 (6)

28

reserved

 

A5

6

33 (27)

13 (7)

36

SS

 

A6

7

32 (26)

14 (8)

33

reserved

 

--

40

31 (25)

15 (9)

30

Vcc

 

Vss

20

30 (24)

16 (10)

23

SBI

 

--

39

29 (23)

17 (11)

34

reserved

 

--

38

28 (22)

18 (12)

19

TM

 

--

37

27 (21)

19 (13)

13

SDOUTA

 

SDOUTB

15

26 (20)

20 (14)

16

reserved

 

--

32

25 (19)

21 (15)

11

SCOA

 

SCOB

12

24 (18)

22 (16)

20

Vss

 

Vcc

30

23 (17)

NOTE: A pin number in square brackets, i.e. [29] means that this ALL03 pin is buffered with 2 gates of 74LS14 in series (thus not inverting the signal). Supply for the 74LS14 (14 = Vcc, 7 = Vss) comes from ALL-03 pins 30 and 20 respectively.

other links :

Enable jtag if device has JTAG disabled

https://www.eevblog.com/forum/fpga/programming-(non-jtag)-max7000-devices/?all

https://forum.system-cfg.com/viewtopic.php?f=18&t=13192

 

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