,57
0,1,7,-1,9,16,
1,1,7,-1,9,
2,1,7,-2,
3,1,7,-3,
4,1,7,-4,-5,9,-6,
5,2,8,7,-7,15,
6,2,8,7,-8,15,
7,2,10,11,12,-9,13,-10,14,-11,14,-12,15,
8,1,7,-13,-14,-15,-16,-17,-18,-19,
9,1,-20,-21,-22,7,
10,1,7,
11,1,7,-23,16,
12,1,7,-23,
13,1,7,-24,16,
14,1,7,-24,
15,1,7,16,
16,1,6,-25,7,-26,18,
17,1,6,-25,7,-26,18,19,20,
18,1,7,-27,
19,1,7,-28,
20,1,7,-27,17,
21,1,7,-29,
22,2,7,-30,
23,25,-31,5,6,-32,
24,1,6,-32,17,
25,1,7,-33,
26,1,7,-34,
27,1,7,-35,21,17,
28,1,7,-35,
29,1,26,-36,8,-37,22,-38,-39,-40,17,
30,1,26,-41,8,-42,23,-43,22,-44,17,24,
31,2,8,7,-8,
32,2,10,11,12,-9,13,-10,14,-11,14,-12,
33,1,
34,27,28,29,30,31,32,
35,1,33,-45,
36,34,6,
37,2,35,
38,2,36,35,37,
39,2,3,37,38,
40,39,40,41,
41,1,6,
42,1,7,42,
43,1,7,42,43,
44,1,44,15,45,46,47,
45,1,7,15
46,1,7,16,
47,2,-46,-47,48,49,50,51,52,15,
48,1,7,15,46,
49,53,54,55,56,57,58,59,60,
50,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68
51,1,69,70,
52,71,72,73,74,75,76,-48,77,-49,17,
53,1,7,78,7
54,1,44,79,45,80,47
55,1,81,79
56,1,83,15,82,46,84

1,Array fuses.
2,AND/OR array fuses.
3,AND array fuses.
4,OR array fuses.
5,Control term fuses.
6,Polarity fuses(XOR).
7,architecture fuses.
8,Global cell fuses.
9,Miser bit fuses.
10,FPLA CTRL array fuses.
11,PAL AND/CTRL array fuses.
12,ILMC array fuses.
13,IMUX array fuses.
14,OLMC/PLMC array fuses.
15,UES fuses. 'A'to ASCII edit
16,TURBO bit fuses.
17,Signature fuses. 'A'to ASCII edit
18,Config fuse.
19,Synchronous preset fuses.
20,Asynchronous reset fuses.
21,Zero bit fuse.
22,Logic control and I/O cell fuses.
23,Input configuration fuses.
24,Gate bit fuse.
25,AND/OR logic or product term fuses
26,Product term fuse.
27,I/O logic cell universal fuses
28,I/O logic cell regional fuses
29,buried logic cell universal fuses
30,buried logic cell regional fuses
31,I/O logic cell configuration fuses
32,buried logic cell configuration fuses
33,feature cell fuses
34,Logic term or product term fuses
35,PR(INIT)/OE option fuses
36,clk2 fuses
37,Preset/reset fuse
38,FCS option fuses
39,Main array term fuses
40,Clock array term fuses
41,Configuration function term fuses
42,I/O configuration bits
43,Clock configuration bits
44,XOR bits
45,AC1 bits
46,Product term disable fuses
47,SYN and AC0 bits
48,OE array fuses
49,Reset product term fuses
50,Input logic macrocell fuses
51,Output logic macrocell fuses
52,Other input macro cell fuses
53,Array fuses A block
54,Achitecture fuses A block
55,Array fuses B block
56,Achitecture fuses B block
57,Array fuses C block
58,Achitecture fuses C block
59,Array fuses D block
60,Achitecture fuses D block
61,Array fuses E block
62,Achitecture fuses E block
63,Array fuses F block
64,Achitecture fuses F block
65,Array fuses G block
66,Achitecture fuses G block
67,Array fuses H block
68,Achitecture fuses H block
69,Achitecture fuses
70,Achitecture PIM fuses
71,PCLKA and RTA
72,AND Array and OR1 Array
73,AND Array and OR2 Array
74,PCLKB,RTB and PCLKC
75,Global Configuration G0-G10
76,Input Configuration H0-H1
77,LCC and I/O Macro Configuration
78,Security bit (Ignore for edition)
79,USER Row. 'A'to ASCII edit
80,PTD Row
81,S0 bits and S1 bits
82,CL0 bits
83,CL1 bits
84,CG0 and CG1 bits
-1,L17028 PIN 28-23,20-15 (C0-C3,C0-C2),L17070 PIN 2-7,9-14 (C4)
-2,PIN 28-23,20-15 (C0-C2,C0-C1)
-3,L9600 PIN 1,2 (LC0,LC1,LC3),L9606 PIN 3-7,9-14 (LC0-LC3)
-4,L9650 PIN 28-23,20-15 (RC0-RC4)
-5,(MB0-192)
-6,L14568 S0-2(PB0-2,B0-7,IO11-0,O0-3) L14649 S3(B0..O3) L14673 S4-5(IO11..O3)
-7,L14568 S0-2 (PB0-2,B0-7,I/O11-0,O0-3) L14649 S3-5 (B0..O3)
-8,S0-S4 (ILMC12-ILMC27)
-9,L20216 S0 (FPLA0-31,PAL0-23,CLK),L20273 S1 (FPLA0-31)
-10,S0-S8 (PLMC0-2,OLMC8-31,OLMC0-7)
-11,S9-11 (OLMC8-31)
-12,MACRO CELL 1-8 (O1-O4,F1-F3)
-13,O1-->OUTPUT by Negative Combinational
-14,O2-->OUTPUT by Positive Combinational
-15,O3-->OUTPUT by Negative Register
-16,O4-->OUTPUT by Positive Register
-17,F1-->FEEDBACK from OR gate
-18,F2-->FEEDBACK from Register
-19,F3-->FEEDBACK from output pin
-20,Address from 2592 to 2879=Referance Array bits used to optimize device
-21,performance(all must be programed to the \" no-connect\" state prior to
-22,device operation.
-23,CELL 1-16 (INV,OECK,DFF,PFB,COUT)
-24,CELL 1-24 (INV,OECK,DFF,PFB,COUT)
-25,B0-B7
-26,AC1,AC2
-27,S0,S1
-28,L5808-L5827 (S0,S1),L5828-L5837 (S2)
-29,S0,S1,S3
-30,/OE,CLK,POLARITY (Rn0-Rn7)
-31,Row for product term, Column for input line
-32,XOR 0-9 (PIN 19,18,17,16,15,14,13,12,11,9)
-33,PIN 19-12 (A,B,C,D)
-34,PIN 23-14 (A,B)
-35,PIN 23-14 (A,B,C,D)
-36,PCLKA,PCLKB,RegTypeA,B(Register Type for Group A,B Global Cell
-37,Group A and B Global Cells(Configuration Bits G0-G3)
-38,PIN (2,14)(3,15)(4,16)(5,17)(6,18)(7,19)(8,20)(9,21)(10,22)(11,23)
-39,Logic Control cell L0-L3 (PIN 2) L0-L3 (PIN 14) ,L4-L7(PIN 2)
-40,L4-L7(PIN 14) ,L8 I/O Cell I0-I2(PIN 2) L8 I/O Cell I0-I2(PIN 14)
-41,PCLKA,PCLKB,RegType product term
-42,G0-G7
-43,PIN 2-6 8-14 (H0,H1)
-44,PIN 15-20 22-27 (L0-L7,I0-I3,L8)
-45,c0-c2(c0:OR, c1:XOR, c2:POLARITY) PIN 12-19
-46,column 0-77 AND fuses
-47,column 78-113 OR fuses
-48,Pin 6-16,18,28-38,40
-49,L0,L1,L2,L3,L4,L5,L6,L7,I0,I1,I2,I3,L8