DEVICE        39V18;

/*   The title keyword is optional. If present the string following will be */
/* printed on the top of each page of the document file.                    */
TITLE        39V18 DESIGN EXAMPLE FOR LOGIC COMP;

/*   The name keyword works just like the title keyword                     */
NAME        10 BIT PARALLEL LOAD COUNTER;

/*   Signature is optional. If present the string following will be placed  */
/* in the device signature fuses in the JEDEC file. If the device you have  */
/* specified has no signature fuses this will be ignored.                   */
SIGNATURE    COUNT_39V;

/* ------------------------------------------------------------------------ */
/* only the pins you use need to be defined                                 */
/* ------------------------------------------------------------------------ */

PIN    1     =    LOAD;
PIN    2     =    L0;
ZPIN    3     =    L1;
PIN    4     =    L2;
PIN    5     =    L3;
PIN    6     =    L4;
PIN    7     =    L5;
PIN    8     =    L6;
PIN    9     =    L7;
PIN    10    =    L8;
PIN    11    =    L9;
PIN    12    =    GND;
PIN    13    =    CLK;        /* NO SUM TERM CLOCKS IN THIS PART  */
PIN    14    =    C9;        /* MOST SIGNIFICANT BIT OF COUNTER  */
PIN    15    =    C8;
PIN    16    =    C7;
PIN    17    =    C6;
PIN    18    =    C5;
PIN    19    =    C4;
PIN    20    =    C3;
PIN    21    =    C2;
PIN    22    =    C1;
PIN    23    =    C0;
PIN    24    =    VCC;

/* ------------------------------------------------------------------------ */
/*                                                                          */
/*  Nodes are like pins but are internal to the device. A node might refer  */
/* to a product term ( reset ) a sum term or a single fuse.                 */
/*                                                                          */
/* ------------------------------------------------------------------------ */

NODE 115    =    RESET;
NODE 116    =    INSYN;
NODE 117    =    INLATCH;
NODE 118    =    IOSYN;
NODE 119    =    IOLATCH;

/* ------------------------------------------------------------------------ */
/*                                                                          */
/*  Pin modifiers can be used to refer to a function associated with a pin. */
/* In the example below .OE refers to an output enable term controlling the */
/* output buffer of the associated pin. ( 14.OE controls ouput pin 14). A   */
/* value of VCC specifies setting the entire product term to 1. A value of  */
/* GND specifies setting the entire product term to 0. Note the value VCC   */
/* or GND must match the spelling in the pin list.                          */
/*  Note the .OE equations are not necessary as this will be the default    */
/* for output pins which are used in equations.                             */
/*                                                                          */
/* ------------------------------------------------------------------------ */

 C0.OE    = VCC;
 C1.OE    = VCC;
 C2.OE    = VCC;
 C3.OE    = VCC;
 C4.OE    = VCC;
 C5.OE    = VCC;
 C6.OE    = VCC;
 C7.OE    = VCC;
 C8.OE    = VCC;
 C9.OE    = VCC;

/* ------------------------------------------------------------------------ */
/*                                                                          */
/* ------------------------------------------------------------------------ */

RESET    = VCC;

/* ------------------------------------------------------------------------ */
/* The counter equations are basically T flip-flops with parallel load      */
/* ------------------------------------------------------------------------ */

/*           toggle    or  load                                             */
C0.D    = !C0.Q & !LOAD | L0 & LOAD;
C1.D    = !C1.Q & !LOAD | L1 & LOAD;
C2.D    = !C2.Q & !LOAD | L2 & LOAD;
C3.D    = !C3.Q & !LOAD | L3 & LOAD;
C4.D    = !C4.Q & !LOAD | L4 & LOAD;
C5.D    = !C5.Q & !LOAD | L5 & LOAD;
C6.D    = !C6.Q & !LOAD | L6 & LOAD;
C7.D    = !C7.Q & !LOAD | L7 & LOAD;
C8.D    = !C8.Q & !LOAD | L8 & LOAD;
C9.D    = !C9.Q & !LOAD | L9 & LOAD;

/* ------------------------------------------------------------------------ */
/*   These equations take advantage of the 39v18s unique characteristics    */
/* The E sum term can be used one of two ways. Here we are using it as a    */
/* control for the clocking of the D registers. Registers will be clocked   */
/* only when the associated E sum term is true. If the E sum term if not    */
/* true the clock line is ignored.                                          */
/*   Since the above equations cause the output to toggle when clocked the  */
/* E sum term is basically the input to a T flip flop. When E (T) = 1 the   */
/* output toggles with every clock; When E (T) = 0 the output remains the   */
/* same                                                                     */
/* ------------------------------------------------------------------------ */

C0.E    =  VCC;
C1.E    =  C0.Q | LOAD;
C2.E    =  C1.Q & C0.Q | LOAD;
C3.E    =  C2.Q & C1.Q & C0.Q | LOAD;
C4.E    =  C3.Q & C2.Q & C1.Q & C0.Q | LOAD;
C5.E    =  C4.Q & C3.Q & C2.Q & C1.Q & C0.Q | LOAD;
C6.E    =  C5.Q & C4.Q & C3.Q & C2.Q & C1.Q & C0.Q | LOAD;
C7.E    =  C6.Q & C5.Q & C4.Q & C3.Q & C2.Q & C1.Q & C0.Q | LOAD;
C8.E    =  C7.Q & C6.Q & C5.Q & C4.Q & C3.Q & C2.Q & C1.Q & C0.Q | LOAD;
C9.E    =  C8.Q & C7.Q & C6.Q & C5.Q & C4.Q & C3.Q & C2.Q & C1.Q & C0.Q | LOAD;