DEVICE		39V18ES;

/*   The title keyword is optional. If present the string following will be */
/* printed on the top of each page of the document file.                    */

TITLE        39V18 DESIGN EXAMPLE FOR LOGIC COMP;

/*   The name keyword works just like the title keyword                     */

NAME        10 BIT PARALLEL LOAD COUNTER;

/*   Signature is optional. If present the string following will be placed  */
/* in the device signature fuses in the JEDEC file. If the device you have  */
/* specified has no signature fuses this will be ignored.                   */

SIGNATURE    COUNT_39V;

/* ------------------------------------------------------------------------ */
/* only the pins you use need to be defined                                 */
/* ------------------------------------------------------------------------ */

PIN    11    =    RST;

PIN    14    =    C0;                   /* LEAST SIGNIFICANT BIT OF COUNTER */
PIN    15    =    C1;
PIN    16    =    C2;
PIN    17    =    C3;
PIN    18    =    C4;
PIN    19    =    C5;
PIN    20    =    C6;
PIN    21    =    C7;
PIN    22    =    C8;
PIN    23    =    C9;
PIN    24    =    VCC;

/* ------------------------------------------------------------------------ */
/*                                                                          */
/*  The keyword buried is used to refer to buried pins.                     */
/*                                                                          */
/* ------------------------------------------------------------------------ */

BURIED    25    =    CA;
BURIED    26    =    CB;
BURIED    27    =    CC;
BURIED    28    =    CD;
BURIED    29    =    CE;
BURIED    30    =    CF;
BURIED    31    =    C10;
BURIED    32    =    C11;		/* MOST SIGNIFICANT BIT OF COUNTER  */

/* ------------------------------------------------------------------------ */
/*                                                                          */
/*  Nodes are like pins but are internal to the device. A node might refer  */
/* to a product term ( reset ) a sum term or a single fuse.                 */
/*                                                                          */
/* ------------------------------------------------------------------------ */

NODE 115    =    RESET;			/* refers to the RESET product term */

/* ------------------------------------------------------------------------ */
/*                                                                          */
/* ------------------------------------------------------------------------ */

RESET	= RST;

/* ------------------------------------------------------------------------ */
/* These equations should produce an 18 bit counter ( with 8 bits buried ). */
/* Each output is being used as a 'T' flip flop.                            */
/* ------------------------------------------------------------------------ */

C0.D	= !C0.Q;
C1.D	= !C1.Q;
C2.D	= !C2.Q;
C3.D	= !C3.Q;
C4.D	= !C4.Q;
C5.D	= !C5.Q;
C6.D	= !C6.Q;
C7.D	= !C7.Q;
C8.D	= !C8.Q;
C9.D	= !C9.Q;
CA.D	= !CA.Q;
CB.D	= !CB.Q;
CC.D	= !CC.Q;
CD.D	= !CD.Q;
CE.D	= !CE.Q;
CF.D	= !CF.Q;
C10.D	= !C10.Q;
C11.D	= !C11.Q;

/* ------------------------------------------------------------------------ */
/* pinname.CK causes the E sum term associated with 'pinname' to be the     */
/* source of the clock for the corresponding OLMC or SLMC. In this example  */
/* the output of each stage becomes the clock for the next stage forming a  */
/* ripple counter                                                           */
/* ------------------------------------------------------------------------ */


C1.CK	=  C0.Q;
C2.CK	=  C1.Q;
C3.CK	=  C2.Q;
C4.CK	=  C3.Q;
C5.CK	=  C4.Q;
C6.CK	=  C5.Q;
C7.CK	=  C6.Q;
C8.CK	=  C7.Q;
C9.CK	=  C8.Q;
CA.CK	=  C9.Q;
CB.CK	=  CA.Q;
CC.CK	=  CB.Q;
CD.CK	=  CC.Q;
CE.CK	=  CD.Q;
CF.CK	=  CE.Q;
C10.CK	=  CF.Q;
C11.CK	=  C10.Q;