Top-level entity/configuration- Enter an optional entity or configuration name. If entered, this name will
override the default top-level entity.
Top-level architecture - Enter an optional architecture name. If entered, this name will override the default
top-level architecture.
Library mapping - Use this option to specify the use of libraries in your project.
The Synthesis tool expects all user-defined libraries to be provided in the form of VHDL source files. If you are
using a library name that differs from the name of the corresponding VHDL source file(s), then you must use the
Library mapping option to specify the relationship between a library and its corresponding VHDL source files. You
must specify libraries in this field using the form:
libname1 vhdfile1 vhdfile2 vhdfile3; libname2 vhdfile4 vhdfile5;
where 'libname1' and 'libname2' are library names, and 'vhdfilen' refers to the specific VHDL source file names
that are to be analyzed to form the specified library. For example, if you have defined a library named "mylib"
that contains packages "fred" and "barney", which are themselves described in VHDL files named
"fred1.vhd" and "barney1.vhd", you would enter the following information into the Library mapping
field:
mylib fred1.vhd barney1.vhd
Library mapping:
Include IEEE numeric_std package - Select this
option if your project makes use of the IEEE 1076.3 numeric_std package.
Include Synopsys library - Select this option if
your project makes use of the std_logic_arith package or other Synopsys packages. |

Synthesis options: Optimization level [default value (3)]: The valid range is 0 through 5. Select
a value corresponding to the level of effort the synthesizer should put into combinational logic optimization.
Higher numbers specify more extensive optimization, at the expense of additional run time/memory. Lower values
indicate that lesser optimizations will be performed. Select lower values if the optimization takes an unreasonable
amount of time to complete. A value of zero (0) indicates that no combinational logic optimization is to be performed.
Generate CE Logic - Select this option if your
logic requires you to use Clock Enable Logic. The Fitter can run into a problem if a Product term (PT) is used
as a Clock and another PT is used for CE. The ATF15xx architecture uses the same PT for CLK and CE. It works well
if the Clock is using a Global Clock pin. |