Logic Synthesis


Logic Synthesis applies to both VHDL and Schematic/Cupl flows.

Input Files: VHDL (.vhd) or Schematic(.sch)/CUPL (.pld) Source Files. At this time mixed mode entry that allows for both VHDL source files and Schematic/CUPL source files is not supported. The flows for each type of file are pre-defined through the Prochip Design Manager.

Action: VHDL flow: Synthesis will convert the VHDL Source code into an EDIF file. The default tool is Protel Metamor Synthesis tool.

Schematic/Cupl flow: Synthesis will convert a .sch/.pld file into a .PLA(.tt2) file. The default tool is Protel Design Explorer 99SE.

Output: VHDL flow: EDIF file. This will be the TOP level VHDL filename.edf

Schematic/Cupl flow: PLA file. This will be the TOP level CUPL file filename.pla(.tt2)


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