Vantis' DesignDirect-CPLD Release Notes       Updated: 16 April, 1999
Release Version R1.1.017
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

This document contains the following sections:

	Overview
	Minimum PC System Requirements
        What's new in Version 1.1
	Installation from CD
		Instructions
		Additional Notes
		CAE Library
	Software Registration and Licensing
	What's New in this Version
	Known Problems in 1.0, Resolved in 1.1
	Known Problems and Solutions in 1.1
		Installation Issues
		Licensing Issues
		Device Support Issues
                Timing Analysis Issues
		General Issues
		LeonardoSpectrum
		ModelSim
	Third Party Support
	Macro Support
	VantisPRO Software
	Technical Support


=====================================================================
Overview
=====================================================================
Welcome to Vantis' DesignDirect software!

This software consists of the complete DesignDirect development 
system.  You have all the software needed to design, implement, 
simulate and program all Vantis MACH and PAL devices in one, easy to 
use system. 

The Vantis 1999 DataBook is also included for quick access to our 
latest datasheets, application notes and product information.
For the latest information on Vantis products, please visit 
the Vantis WEB site:  
        http://www.vantis.com

Adobe Acrobat Reader is also included for displaying documentation. 

DesignDirect Vista and Summit versions also include Synthesis and 
Simulation (RTL and Timing) capabilities.

Note that to use the DesignDirect software, you must read and accept
the Vantis Software License Agreement displayed during installation. 


=====================================================================
Minimum PC System Requirements
=====================================================================
AMD K6, Pentium or equivalent
Windows '95, '98 or NT 4
32 Mb RAM (System performance improves with more memory)
CDROM reader (for CDROM installation)
300 Mb free hard disk space (for installation)
  Actual size of programs are:
    80MB - DesignDirect Base
   130MB - DesignDirect Vista and Summit
Mouse or pointing device
HTML/WEB browser (for viewing databook)
Adobe Acrobat Reader 3.0 or higher (for viewing tutorials & 
DataBooks)


=====================================================================
What's New in Version 1.1
=====================================================================
DesignDirect 1.1 version contains the following new features:

1.  Vantis' version of Exemplar's Synthesis tool:
    LeonardoSpectrum for Vantis 
	(supported in Vista or Summit systems only).
2.  Vantis' version of Model Technology Simulator, 
    ModelSim Personal Edition Vantis Version 
        (supported in Vista or Summit systems only).
3.  Support for M4A-384/192 and M4A-512/256 devices (without JEDEC or
    BGA support.  Only -7 Timing)
4.  Improved optimization algorithms.
5.  Updated MACHPRO 2.00o to VantisPRO 3.00c.
      - This version has March 25, 1999 updated JTAG files
        (refer to JTAGPART.TXT file under \VANTISPRO\JTAG directory)
6.  Added support to run multiple release versions of DesignDirect on
    the same computer.

  The following Application notes have been posted on the Vantis web 
  www.vantis.com :-
       Finite State Machine coding guidelines for synthesis
       D/T Flip flop Synthesis guidelines.

Note:  If you already have license for DesignDirect, the same license
       code will work for this DesignDirect version.  If you wish to
       upgrade your base System to Vista or Summit, please contact 
       your local Vantis sales office.    


=====================================================================
Installation from CD
=====================================================================
Instructions
~~~~~~~~~~~~
1. Exit all open Windows applications and insert CD into CD-ROM drive
2. Click the START button and select RUN
3. Type CD-ROM drive letter, then :\pc\ddirect\setup.exe
   (e.g. e:\pc\ddirect\setup.exe)
4. Follow the on-screen installation instructions
5. After installation is complete, click on DesignDirect-CPLD 1.1 
   Licensing in the DesignDirect program folder to open the 
   license.dat file.  
   (START->PROGRAMS->DesignDirect-CPLD 1.1->DesignDirect-CPLD 1.1
   Licensing).  Follow the instructions contained in the license.dat 
   file to register the software and obtain the license code.
6. From the DesignDirect Project Manager, select HELP->TUTORIALS to 
   learn how to use DesignDirect software.
7. Pass this CD on to your colleagues so they can install a free copy
   of the DesignDirect Base development system on their PCs.

Note: If you are upgrading your Base system to Vista or Summit, 
      please remember to save your previous base license under a 
      different name.  The default location  of this file is
      c:\Vantis\cpld11\license\license.dat

Additional Notes
~~~~~~~~~~~~~~~~
1. During installation, DesignDirect-CPLD will register into the 
   Windows Registry. It requires Read/Write access to the 
   Windows Registry
   "HKEY_CLASSES_ROOT".  

   For Windows-NT, the "HKEY_CLASSES_ROOT must be accessible during
   installation.  If you do not have Read/Write privilege to this
   registry key, then a system administrator can either re-configure
   your system to allow this privilege, or he/she can install the
   software for you.  

   Note: Once a system administrator installs the software, 
   DesignDirect software is automatically installed into the Common 
   program folder, allowing any user to run the software.

         For a user who has Read/Write privilege to 
         "HKEY_CLASSES_ROOT"
         registry key, DesignDirect will be installed into the 
         Personal program folder.

CAE Library
~~~~~~~~~~~
DesignDirect will create a CAE directory with the following libraries
installed:
       - VITAL (\CAE\VITAL\)
       - Verilog (\CAE\Verilog\)
       - Viewlogic (\CAE\WV\) 


=====================================================================
Software Registration and Licensing
=====================================================================
DesignDirect-CPLD requires a license from Vantis.  You will be 
required to register your software via the Vantis WEB-based 
registration. 

For Software Registration instructions, refer to the LICENSE.DAT 
file, accessed via "DesignDirect-CPLD Licensing" icon in the 
DesignDirect-CPLD Windows program folder.


=====================================================================
Known Problems in Version 1.0, Resolved in 1.1
=====================================================================
Installation Issues
~~~~~~~~~~~~~~~~~~~
1.  In some Windows 95 systems, the installation process seems to 
    hang up.
    Resolution:  Your virus checker program may be hindering the 
                 installation process.  Unload or disable this 
                 program.
    Workaround:  If the above resolution does not resolve this 
                 problem, open the Task Manager 
                 press <Ctrl><Alt><Del> keys simultaneously, and 
                 terminate the process "_DELIS.EXE".
                 Once this process is terminated, the installation 
		 should proceed without any problems.

General Issues
~~~~~~~~~~~~~~
1.  For some MACH 4 and 4A designs, fitter encountered re-fit 
    problem for "Pin Assignments" option in "Backannotate Project 
    Assignments" dialog.

2.  For some designs, the Generate Timing Simulation Files process 
    failed to generate the timing files (VHDL, Verilog or EDIF, and 
    SDF or DTB formats).

3.  Fixed missing E and U fields in JEDEC file created for
    M4-128N/64 device.

4.  Added missing VCC symbol in the ModelSim simulation library.

5.  Fixed Import Source Constraint bug where the pin type was 
    incorrectly specified (illustrated in Constraint Editor as 
    highlighted in red).

6.  Fixed problem in the Constraint Editor, imported pins assignments
    were incorrectly highlighted in red. 


8.  WS2_HELP.DLL, WS2_32.DLL Compatibility Problem:  For Windows NT,
    if you get compatibility issue with the above DLLs,
    try the following:
      - Remove or rename the WS2_HELP.DLL and WS2_32.DLL in the
        DesignDirect-CPLD root directory.   

9.  EDIF reader problem: When you read an existing DesignDirect 
    project with an imported EDIF file, you may get "Unable to create
    Hierarchy" error.  To resolve this problem, do the following:
      - Remove the EDIF source from the project via the Source-Remove
        command.
      - Re-import the same EDIF file into the project via 
        Source-Import.

10. Resolved JEDEC file problems for some Mach 1 and 2 devices.


Timing Analysis Issues
~~~~~~~~~~~~~~~~~~~~~~
1.  Resolved the incorrect values for the following devices:

    MACH231 -6 (commercial temp):
    The value of tPL max in the software was 10ns. It is now 
    corrected to be 9ns.

    MACH211/221:
    The value of tPDLi in the software was too large. It
    included the output buffer delay, tBUF. Corrected in version 1.1.

    MACH5A family -6 (commercial temp):
    The value of tWIRH in the software was 4ns. It is now
    corrected to be 3ns.

    MACH5 family
    The value of tGOSi/tGOAi is too large. It included the 
    output buffer delay, tBUF. Corrected in version 1.1.


Design problems Resolved: 
~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Problem: Design failed to fit but, no errors were listed in 
             the automake.log.
    Resolution: Fix to Report Generator.

    Problem: Inverted clocks mistaken as PTERM clocks for M5 devices.
    Resolution: Fix to appropriate .dll.

    Problem: Design failed during fit if tilde (~) was used in 
             identifier.
    Resolution: Fix to Fitter Engine.

    Problem: When targeting pals with a schematic design, the tool
             could not get past the reduce schematic process.
    Resolution: Fix to Optimizer.

    Problem: When assigned only pins on a MACH 4 device, software 
             also assigned macrocells.
    Resolution: Fix to Fitter Module.

    Problem: In ABEL hierarchical designs, the pre-fitter equations 
             are not optimized.
    Resolution: Fix to Optimizer.


=====================================================================
Known Problems and Solutions with version 1.1
=====================================================================
Installation Issues
~~~~~~~~~~~~~~~~~~~

  Problem: The Host ID isn't written to the license.dat file
  Solution : If the Host ID is not written into the LICENSE.DAT 
       file, run the VALID.EXE program in the VANTIS\CPLD directory 
       (under DOS or Command Prompt mode) to get the HOST ID.

Licensing Issues
~~~~~~~~~~~~~~~~
  Problem: The license file from Vantis doesn't work.
  Solution: What to do if the License codes from Vantis do not work.
    The email sent from Vantis that includes the License codes 
    contains TAB characters in the codes.  

    a. Some email tools substitute the TAB characters with Dashes or
       "-".  You will need to replace the "-" characters with TAB 
       characters manually.

    b. If you use MS WORD as an editor for your MS Outlook email, it 
       is possible that the double quote or equal characters (" or =)
       will be converted into TAB or unprintable characters when you
       are doing Cut & Paste.  There were also reports that the disk 
       ID in the License code were corrupted.

    c. Here is an example of the correct License codes:

PACKAGE 3p vantisd 4.0 23DFFFF00B7C COMPONENTS="49 50 256 260 261 \
		263 269 271 272 512 516 538" OPTIONS=SUITE
PACKAGE 5p vantisd 4.0 36FFFF2D89DF COMPONENTS="261 512 515 538" \
		OPTIONS=SUITE
FEAURE 3p vantisd 4.0 permanent uncounted BF75ABC274EC8 \
		HOSTID=DISK_SERIAL_NUM=3cf56d12 SUITE_DUP_GROUP=UH
FEATURE 5p vantisd 4.0 permanent uncounted 656ABC2BF369 \
		HOSTID=DISK_SERIAL_NUM=3cf56d12 SUITE_DUP_GROUP=UH

       In above License codes, DISK ID = 3cf56d12.

    
Device Support Issues
~~~~~~~~~~~~~~~~~~~~~

  Problem: M4A3, M4A5, M5A3 & M5A5 aren't selectable
  Solution: Choose the M4A and M5A families instead.


Timing Analysis Issues
~~~~~~~~~~~~~~~~~~~~~~
1. Reset and recovery time for a register is reported in the tSU
   Analysis.

  Problem: The software timing model parameter names for the MACH1 
    and MACH2 families are different from the parameter names 
    appearing in the datasheets. 
  Solution: The cross reference chart appears below:

   Data Sheet		Software Model
   Parameter		Parameter

   tPD			tPDi + tBUF
   tS(D-type)		tSS
   tS(T-type)		tSST
   tH			tHS
   tCO			tCOSi + tBUF
   tWL			tWLS
   tWH			tWHS
   tSL			tSSL
   tHL			tHSL
   tGO			tGOSi + tBUF
   tGWL			tGWS
   tPDL			tPDLi + tBUF
   tSIR			tSIRS
   tHIR			tHIRS
   tICO			tICOSi + tBUF
   tWICL		tWIRL
   tWICH		tWIRH
   tIGO			tIGOSi + tBUF
   tWIGL		tWIL
   tAR			tSRi + tBUF
   tAP			tSRi + tBUF
   tARW			tSRW
   tAPW			tSRW
   tARR			tSRR
   tAPR			tSRR

   Parameter names with the "i" subscript (e.g. tPDi) represent
   internal delays. The output buffer delay tBUF is added to the
   internal delay to calculate the external pin-to-pin delays.

   The value of tBUF used by the software is calculated
   as shown below:

   From databook:

   fMAX = 1/( tS + tCO )
   fCNT = 1/( tS + tCOi )

   Therefore,

   tBUF = tCO - tCOi  = 1/fMAX - 1/fCNT 

     
General Issues
~~~~~~~~~~~~~~
  Problem: Design fails to fit with the error message 
    "Logical Error 3512: Signal 'sig1' in module 'mod1' has an OE.  
    An output wire is required for that signal."
  Solution: If a signal has an Output Enable control but is declared
    as a node, this error message will result.  To rectify this issue,
    change the signal from a node to an output.

  Problem: DesignDirect does not support directory or file names with 
    spaces.
  Solution: Name all your working files with standard DOS names and
    extensions.  

  Problem: Assignment of power levels in M5 devices
  Solution: To assign a power level to a block (other than the default 
    setting) there must be at least one pin or node assigned to that
    block.

    You can assign the pins or nodes manually, or you can let the 
    fitter make the assignments. If you let the fitter make the 
    assignments, be sure to backannotate the pins and blocks before 
    assigning block power levels.
    
  Problem: Attributes from Synplicity and FPGA Express aren't 
    supported.
  Solution: At this time, Synplicity and Synopsys FPGA Express 
    Synthesis tools do not place any attributes/constraints in the 
    EDIF file for DesignDirect. Use the DesignDirect CPLD Constraints
    Editor to specify constraints.

  Problem: Constraint Editor & Performance Analyst are not supported 
    for PAL devices.
  Solution: Performance Analyst, Constraint Editor and GUI dialog 
    boxes are supported for MACH devices only.  These features are 
    not supported for PAL and PALLV family.

  Problem: Performance Analyst gives an application error when the 
    Project Manager is closed without first closing the Performance 
    Analyst window.  
  Solution: Close the Performance Analyst first.  This problem does 
    not affect the Project Manager or Performance Analyst saved data,
    or the Project Manager design flow.

  Problem: There is no automatic fitter for the PALCE29M16 and 
    PALCE29MA16 devices
  Solution: For PALCE29M16 and PALCE29MA16 devices, there is no 
    automatic fitter (i.e. no automatic pin assignments).  Pin 
    numbers must be assigned in the source file before the JEDEC file
    can be created.

  Problem: When you do a SaveAs for a project contain an imported 
    EDIF file, you will get "Generate Hierarchy" or Compile EDIF 
    error.
  Solution: Remove the EDIF file from the project and re-import
    the EDIF file into the same project.  

  Problem: The design fails to fit into the selected device.
  Solution: 
    1.  Open "Global Project Optimization" option. Select
	 "Logic Synthesis" tab.
    2.  Under Node Collapsing, select "Collapse Selectively 
        (for density)" option.
    3.  Set Product Terms for Collapse Equations and Split Equations
        to device maximum. Click on the Up arrow to increment to 
        number. Once the number stops incrementing, the maximum 
        number is achieved.
    4.  Re-run the DesignDirect Fitter.



LeonardoSpectrum Issues
~~~~~~~~~~~~~~~~~~~~~~~

  Problem: What does the Alternate MACH flow do?
  Solution: This is a different optimization algorithm.  As a rule
    of thumb, better results are obtained with this switch off.

  Problem: DesignDirect will not import an edif with a part name
    of greater than 8 characters.
  Solution: Name the HDL files with standard DOS naming and 
    extensions.

  Problem: VHDL pin attribute cannot be applied to a bus.
  Solution: The bus must be split-out into STD_LOGIC elements.  
    A pin attribute can then be applied to each pin.


ModelSim Issues
~~~~~~~~~~~~~~~

  Problem: If you start a simulation and then try to restart it, 
    ModelSim returns with an error. 
  Solution: End the simulation and restart it manually. 
  
  Problem: No text editor open before the design passes the 
    compilation. 
  Solution: Enhancement added in a later release.
  
  Problem: In the compilation procedure the 'compile VHDL source' 
    window allows the user to choose the Verilog files but errors 
    out. 
  Solution: Use the 'VLOG' button or 'compile Verilog source' window 
    to compile the Verilog Designs. 
 
  Problem: counter.v in mti example is not synthesisable. 
  Solution  : This is a simulation example only.
  
  Problem: Timing parameter data in simulation is incorrect 
  Solution: Change simulation resolution from nanoseconds to 
    picoseconds.  Using nanoseconds may result in round off errors. 


=====================================================================
Third Party Support
=====================================================================
DesignDirect version 1.1 has been tested for EDIF dialects for:
    
    Exemplar LeonardoSpectrum v1998.2 
    Synopsys FPGA Express v3.0
    Synplicity Synplify v5.08
    Viewlogic 

    DesignDirect will be tested with additional CAE tools in 
    future releases. 


=====================================================================
VantisPRO Software (Formerly called MACHPRO)
=====================================================================
By default, the VantisPRO software is automatically installed with 
the DesignDirect-CPLD software. You can access the VantisPRO software
via the VantisPRO menu command under the Tools menu in 
DesignDirect-CPLD Program Manager, or the VantisPRO icon in the 
DesignDirect-CPLD program folder.

For Windows-NT users:  
  You will require System Administrator privilege to install the 
  driver for the port.  If you have System Administrator privilege, 
  the port driver will be installed during installation. To install 
  the driver after software installation, refer to the README.TXT 
  file in the VANTIS\CPLD\VANTISPRO directory.


=====================================================================
Technical Support
=====================================================================
You can contact Vantis at:
Toll Free: 888-826-8471
USA: 408-616-8044
France: 0800-908521
Germany: 089-450-53199
Italy: 1678-77224
Europe/UK: 44-0-1276-803299
Japan: 03-3346-7550

You can email Vantis at:
USA e-mail: techsupport@vantis.com 
UK/Europe e-mail: euro.tech@vantis.com 

You can visit our Website at:
http://www.vantis.com 

For assistance with the Vantis versions of ModelSim and 
LeonardoSpectrum, please contact Vantis at the number above.
