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FPGA Express: Readme.txt

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~     For late breaking information, checkout the Synopsys Web Site at     ~~~
~~~                       http://www.synopsys.com                            ~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


Here is a list of new features, known last minute problems and their work-
arounds for FPGA Express v1.1, build 1.1.3.6 (see Help->About for build ID)

NEW FEATURES AND BUG FIXES
==========================

* General
---------
- The code between the VHDL directives translate_off and translate_on is
  not analyzed (which is the proper behavior). Previously, the code was
  analyzed (but not synthesized).
  Note: If you expect the code to be analyzed but not synthesized,
  use the VHDL directives synthesis_off and synthesis_on.
   
* Altera (new): FLEX8K, FLEX10K, MAX7K, MAX9K device support
--------------
- EDIF Support (read and write).
- LPM support: FPGA Express
  * Infers LPM for comparators and multipliers for FLEX
  * Infers LPM for all arithmetic operators for MAX
  * Links hand instantiated LPM elements (in VHDL, Verilog or EDIF) to
    VDHL package: <fpga_express dir>\lib\packages\lpm\lpm_components.vhd 
  * Report of estimated area for instantiated LPM elements
- ACF support: FPGA Express
  * Creates an ACF file containing all user constraints
  * Updates existing ACF file (if located in FPGA Express output directory)
    Note: it is recommended not to use an existing ACF file, and let FPGA
    Express create one.
 - Pad location capability (in Ports page).

* Lucent (new): ORCA2A device support
--------------
- EDIF Support (read and write).
- Pad location capability (in Ports page).
- PRF support: FPGA Express exports the user constraints in an SPF file
  This SPF file should be converted to Lucent's PRF file using Lucent's
  spf2prf utility.

* Xilinx (features added)
-------------------------
- A problem with a carry chain generated by FPGA Express, and causing M1 to
  fail, has been fixed.
- A problem with the latch mapping not using the full capability of the
  XC4000EX latch (and therefore using one extra FMAPs in some cases) has
  been fixed.
- The XNF output bus style has been changed from %s_%d to %s<%d>.
- Attribute LIBVER 2.0.0 is not required anymore on user modules.
- Date stamp added in the header of the XNF output ("PROG" field).
- FPGA Express doesn't generate XNF file names with more than 8 characters
  anymore (XMAKE, on PC, couldn't find such a file).


IMPORTANT NOTE
==============
Because this release adds new features and fixes several bugs (listed in
the above section), implementations created with a previous version of
FPGA Express, which are affected by any of the issues mentioned above,
must be re-created in order to use the new engine. To do so, you need to:

* If the existing implementation does not contain any user constraints:
  a- Re-analyze the top level design: select top level file and click
     on Synthesis->Analyze
  b- Create a new implementation
  c- Optimize the implementation

* If the existing implementation contains user constraints:
  1- Save user constraints: double click on the implementation, then select
     File->Export Constraints, and enter a file name for the constraint file
  2- Re-analyze the top level design (see above step "a-")
  3- Create a new implementation
  4- Import constraints: double click on the new implementation, then select
     File->Import Constraints, and browse for the constraint file generated
     in step "1-"
  5- If port names have changed, choose replacement port names using
     the Design Change Wizard. The Xilinx bus notation has changed for
     version 1.1 ("name<number>" instead of "name_number"), so if a design
     has I/O buses, you will be required to choose the corresponding new port
     name for each old port name. The Design Change Wizard spread sheet will
     appear after importing constraints. In the spread sheet, select the signal
     with the new bus notation (from the drop-down list) for each signal which
     previously used the old notation.


KNOWN ISSUES AND WORK-AROUNDS
=============================

* General
---------
1- Reading the HDL and VHDL Reference Manuals:
   The reference manuals are in PDF format and can be viewed using the Adobe
   Acrobat Reader. If you do not have this installed on your system already,
   you may install it from the FPGA Express CD-ROM with the command:
   x:\acrosrch\disk1\setup, where x: represents your CD-ROM drive

2- While FPGA Express is analyzing HDL files, if the STOP button is pushed, the
   analysis will stop after finishing analyzing the current file.  The last file
   being analyzed has the wrong status.
=> Re-analyze the file by selecting it and clicking on Synthesis->Analyze
   Note: clicking on "Analyze All" will not correctly update the status

3- The designs optimized by FPGA Express cannot use the following names:
   AND, XOR, TRI, and SEQ.  These are FPGA Express reserved key words. If
   a design is named using one of these key words, creating implementation
   may fail
=> Rename your design.

4- If you read in two or more source files having design modules with same
   names, FPGA Express may not synthesize the selected module.
=> Before reading in a source file, delete any other source files which
   have design modules which conflict with design modules in the source
   file being read

5- If one or more ports of the top level design are assigned a constant high 
   impedance value 'Z' then optimization will either fail with the error message
   FE-PADMAP-3 or will incorrectly inserts pads between the ports, with no error
   or warning message.
=> For Xilinx, just remove all assignment to high impedance 'Z' in HDL
   description (for all supported Xilinx families an unused pin on the
   chip defaults to a high-impedance value).
   For Altera and Lucent, hand-instantiate a three-state buffer passing
   the high impedance value.

6- When creating implementations for different vendors in the same project,
   the notation of the buses in the design will be inherited from the bus style
   of the first vendor targeted in the project.
   Note: the bus style for Altera is: "%s%d", for Lucent: "%s[%d]" and for
   Xilinx: "%s<%d>"
=> Re-analyze the top level design (select top level file, and click on
   Synthesis->Analyze) before selecting a new vendor.
  
7- A VHDL design containing the directive "translate_off / translate_on"
   may not analyze successfully in FPGA Express 1.1 even though it would in
   previous versions.
=> In 1.1, the code between translate_off and translate_on is ignored,
   while it used to be analyzed (but not synthesized). Just replace
   "translate_off / translate_on" by "synthesis_off / synthesis_on".
   
* Altera:
---------

1- Place and Route may fail with the Error message: "Can't find design file X"
   (where X is a LMF library gate).
=> Select Interfaces->EDIF Netlist Reader Settings->Customize, then
   select the LMF file (<design_name>.lmf) that FPGA Express generated
   in the design output directory.

2- Reading in EDIF netlists written from Maxplus2 may fail
=> The following Maxplus2 switch need to be set:
   Interfaces->Edif Netlist Writer Settings->Customize-> Flatten Bus

3- Undriven nets may lead to problems in Altera's MAX+2
=> Re-write your code to avoid undriven nets.

* Lucent:
---------
1- FPGA Express does not map to synchronous set/reset FFs when the
   target architecture is Lucent.
=> Use Synopsys attributes in the source code to mark signals that are
   to be used as set/reset. See the HDL and VHDL reference manuals for details

   * Verilog example:

     module sync_seq (data, clk, clear, out)
     input data, clk, clear;
     output out;
     reg out;
     //synopsys_sync_set_reset "clear"                     <======
     always @ (clk)
       if (clear)
         out = 1'b0;
       else
         out = data;
     endmodule

   * VHDL example:

     entity sync_seq is 
       port (data  : in std_logic;
             clk   : in std_logic;
             clear : in std_logic;
             out   : out std_logic);
     end sync_seq;

     architecture synth of sync_seq is
     attribute sync_set_reset of clear : signal is "true";  <======
     begin
       process(clk, clear) begin
         if (clk'event and clk = '1') then
            if (clear = '1') then
               out <= '0';
            else 
               out <= data;
            end if;
         end if;
       end process;
     end synth;
 

* Xilinx:
---------

1- Hand instantiated buffers (e.g. BUFGP, BUFGLS, BUFGE) are optimized away
   and possibly replaced by other buffers (e.g. BUFGS).
=> Open the pre-optimized implementation, and set the "Preserve" attribute
   on the module containing the buffers you want to preserve.

2- For XC4000E, FPGA Express may not infer the Global Set Reset (GSR) if
   the design contains latches. Note: this does not happen for XC4000EX.
=> It is recommended not to use latches for XC4000E.