STORY TO SPRINT.087

This is one of the last analysis runs made, when the new SMP key started to
work.

The top 8 traces show the status of the data bus on the card.  Bits 0 to 7 are
found on both pins 2 to 9 as well as 19 to 12.	Remember the PAL reads from and
writes to one common I/O bus.  Other modules on the card have access to the same
bus.  No more than one module should drive the bus at any given time.  Modules
EXPERT A and EXPERT B assure this.

Vertical blips on trace F are I/O write pulses from the PC. When they occur data
is latched from the PC bus into the 74LS374 in socket IA2.
Trace E shows the OE input to this module.  When OE is down, the 74LS374 puts
the written data on the bus.  This occurs most of the time.

Negative going pulses on the D trace indicate when the PC is reading from the
I/O bus.  With the curser on sample #13 we see that the data is coming from the
PAL since trace B shows the level on pin 11 of the PAL (OE) to be negative.
The PAL data travels by way of the card I/O bus and the upper 8 traces show the
contents to be HEX 00.	The 2 rightmost digits of the 4-digit data number on the
right also indicate HEX 00, likewise the 16 bit values to the right of the
traces.  Notice that when the PAL drives the bus, OE of the 74LS374 is
temporarily positive, preventing the 74LS374 from driving the bus at this time.

We see PAL clock pulses on trace C which on the current display coincide with
the +IOW pulses. This means that as the PC data is latched up and retained in
the 74LS374, it is also made available to the PAL for whatever action.

Let us now move the cursor to sample #40 (still with the expansion factor at 4).
The PAL sees HEX 38 and interprets this as a command to set CS in preparation of
a readout of the EEPROM.  The next write (sample #46) drops the data bus back to
HEX 00. CS should stay set for the duration of the EEPROM read operation. A
"maintain" function in the CS equation, using an internal feedback, takes care
of that.

Pulses on trace 4 sure look like SK pulses.  Therefore the PAL interprets HEX 10
as a command to set its SK register and HEX 00 as a command to reset it.  The
contents of this register on the PAL module are not shown, but closely follow
trace 4.

A long succession of 00's is clocked into the EEPROM. I am not sure what the
purpose of this is, may be just a time delay.  The EEPROM takes no visible
action.  It is now looking out to a "start bit" followed by a command.

A couple of "page-ups" bring us to a point where trace 3 is also changing. At
sample #1370 the PAL clocks HEX 08 in as meaning a "one" to be put on DI to the
EEPROM.  We see it appear in sample #1371 on trace 9.  By the way DI data is
read by the EEPROM on the positive transitions of SK.  Apparently, and unknown
to me until this time, the EEPROM acknowledges the receipt of the data on its DO
output.  DO data is clocked out also on the positive transitions of SK.

If we switch to an expansion factor of 1, enter S followed by 1360 and "home",
then the rest of the EEPROM activation can be seen in an overview fashion or in
detail by expanding again.  The start bit is followed by 10 000000, being the
read command HEX 10 and a word address of 000000.  A last zero bit on DI brings
out a dummy zero bit on DO, which is ignored.

It is now time though to take the next bits coming out serious, latch the DO
register in the PAL and read it out by a succession of 16 negative going OE
pulses and IOR's.  The data bit stream, starting at sample # 1536 is 0100 0010
1101 0000 or HEX 42D0 which is exactly what we expected to come out of address
000000 of the C/99 EEPROM.

One of the next obviously visible commands written by the PC to the data bus is
a HEX 05.  This HEX 05 "command" is assumed to be an "end of read" and used to
reset CS by no longer satisfying the "maintain" function in the CS equation.

More PAL clocks and twelve more PAL OE's are visible.  Their purpose is again
unclear, however at the very end of this set of samples we see HEX 38 appear
again, the start of reading word 01 out of the EEPROM.

To give an idea about the time axis:  Samples were taken 500 nanoseconds apart.
The computer running the Sprite card was a 25Mhz IBM PS/1.