EQN2JED - Boolean Equations to JEDEC file assembler (Version V101) Copyright (c) National Semiconductor Corporation 1990-1993 Log file for pal360.eqn Device: 16V8 Pin Label Type --- ----- ---- 1 I0 pos,com input 2 I1 pos,com input 3 I2 pos,com input 4 I3 pos,com input 5 I4 pos,com input 6 I5 pos,com input 7 I6 pos,com input 8 I7 pos,com input 9 I8 pos,com input 10 GND ground pin 11 I9 pos,com input 12 O1 unused 13 O2 unused 14 O3 pos,com output 15 O4 pos,com output 16 O5 pos,com output 17 O6 unused 18 O7 unused 19 O8 unused 20 VCC power pin EQN2JED - Boolean Equations to JEDEC file assembler (Version V101) Copyright (c) National Semiconductor Corporation 1990-1993 Device Utilization: No of dedicated inputs used : 10/10 (100.0%) No of dedicated outputs used : 2/2 (100.0%) No of feedbacks used as dedicated outputs : 1/6 (16.7%) ------------------------------------------ Pin Label Terms Usage ------------------------------------------ 16 O5 1/8 (12.5%) 15 O4 2/8 (25.0%) 14 O3 1/8 (12.5%) ------------------------------------------ Total Terms 4/64 (6.2%) ------------------------------------------ EQN2JED - Boolean Equations to JEDEC file assembler (Version V101) Copyright (c) National Semiconductor Corporation 1990-1993 Chip diagram (DIP) ._____ _____. | \__/ | I0 | 1 20 | VCC I1 | 2 19 | O8 I2 | 3 18 | O7 I3 | 4 17 | O6 I4 | 5 16 | O5 I5 | 6 15 | O4 I6 | 7 14 | O3 I7 | 8 13 | O2 I8 | 9 12 | O1 GND | 10 11 | I9 |______________| EQN2JED - Boolean Equations to JEDEC file assembler (Version V101) Copyright (c) National Semiconductor Corporation 1990-1993 Log file for pal360.eqn Device: 16V8 Pin Label Type --- ----- ---- 1 I0 pos,com input 2 I1 pos,com input 3 I2 pos,com input 4 I3 pos,com input 5 I4 pos,com input 6 I5 pos,com input 7 I6 pos,com input 8 I7 pos,com input 9 I8 pos,com input 10 GND ground pin 11 I9 pos,com input 12 O1 unused 13 O2 unused 14 O3 neg,com output 15 O4 neg,com output 16 O5 neg,com output 17 O6 unused 18 O7 unused 19 O8 unused 20 VCC power pin EQN2JED - Boolean Equations to JEDEC file assembler (Version V101) Copyright (c) National Semiconductor Corporation 1990-1993 Device Utilization: No of dedicated inputs used : 10/10 (100.0%) No of dedicated outputs used : 2/2 (100.0%) No of feedbacks used as dedicated outputs : 1/6 (16.7%) ------------------------------------------ Pin Label Terms Usage ------------------------------------------ 16 O5 2/8 (25.0%) 15 O4 2/8 (25.0%) 14 O3 1/8 (12.5%) ------------------------------------------ Total Terms 5/64 (7.8%) ------------------------------------------ EQN2JED - Boolean Equations to JEDEC file assembler (Version V101) Copyright (c) National Semiconductor Corporation 1990-1993 Chip diagram (DIP) ._____ _____. | \__/ | I0 | 1 20 | VCC I1 | 2 19 | O8 I2 | 3 18 | O7 I3 | 4 17 | O6 I4 | 5 16 | O5 I5 | 6 15 | O4 I6 | 7 14 | O3 I7 | 8 13 | O2 I8 | 9 12 | O1 GND | 10 11 | I9 |______________| EQN2JED - Boolean Equations to JEDEC file assembler (Version V101) Copyright (c) National Semiconductor Corporation 1990-1993 Log file for c:\projets\analyzer\pal360.eqn Device: 16V8 Pin Label Type --- ----- ---- 1 I0 pos,com input 2 I1 pos,com input 3 I2 pos,com input 4 I3 pos,com input 5 I4 pos,com input 6 I5 pos,com input 7 I6 pos,com input 8 I7 pos,com input 9 I8 pos,com input 10 GND ground pin 11 I9 pos,com input 12 O1 unused 13 O2 unused 14 O3 neg,com output 15 O4 neg,com output 16 O5 neg,com output 17 O6 unused 18 O7 unused 19 O8 unused 20 VCC power pin EQN2JED - Boolean Equations to JEDEC file assembler (Version V101) Copyright (c) National Semiconductor Corporation 1990-1993 Device Utilization: No of dedicated inputs used : 10/10 (100.0%) No of dedicated outputs used : 2/2 (100.0%) No of feedbacks used as dedicated outputs : 1/6 (16.7%) ------------------------------------------ Pin Label Terms Usage ------------------------------------------ 16 O5 2/8 (25.0%) 15 O4 2/8 (25.0%) 14 O3 1/8 (12.5%) ------------------------------------------ Total Terms 5/64 (7.8%) ------------------------------------------ EQN2JED - Boolean Equations to JEDEC file assembler (Version V101) Copyright (c) National Semiconductor Corporation 1990-1993 Chip diagram (DIP) ._____ _____. | \__/ | I0 | 1 20 | VCC I1 | 2 19 | O8 I2 | 3 18 | O7 I3 | 4 17 | O6 I4 | 5 16 | O5 I5 | 6 15 | O4 I6 | 7 14 | O3 I7 | 8 13 | O2 I8 | 9 12 | O1 GND | 10 11 | I9 |______________|