this is an 8 bit up/down counter

equations were reduced by ISDATA LOG/iC

Device 24v10

 clock          = 1
 load           = 2
 data0          = 3
 clock2         = 4
 data1          = 5
 data2          = 6
 data3          = 8
 data4          = 9
 data5          = 10
 data6          = 11
 data7          = 12
 down           = 13
/enable         = 15
 cin            = 16    ' carry in
 out4           = 17
 out5           = 18
 out6           = 19
 out7           = 20
 out3           = 22
 out2           = 23
 out1           = 24
 out0           = 25
/sr0            = 26
 sr1            = 27
 reset          = 28

start


/sr0           /:=  /load * sr1  *  sr0            ' 26
		 ;

 out4.ena        = enable;
 out4           :=  /load* down */out4 */out3 */out2 */out1 */out0 * cin
                 +  /load*/down */out4 * out3 * out2 * out1 * out0 * cin
                 +  /load* out4 */cin
                 +  /load* down * out4 * out3
                 +  /load*/down * out4 */out0
                 +  /load* out4 */out1 * out0
                 +  /load* out4 */out3 * out2;

 out5.ena        = enable;
 out5           :=  /load* down */out4 */out5 */out3 */out2 */out1 */out0 * cin
                 +  /load*/down * out4 */out5 * out3 * out2 * out1 * out0 * cin
                 +  /load* out5 */cin
                 +  /load* out4 * out5 */out1
                 +  /load* out5 */out2 * out0
                 +  /load* out5 */out3 * out2
                 +   load* data5;

 out6.ena        = enable;
 out6           :=  /load* down */out4 */out5 */out6 */out3 */out2 */out1 */out0 * cin
                 +  /load*/down * out4 * out5 */out6 * out3 * out2 * out1 * out0 * cin
                 +  /load* out6 */cin
                 +  /load* out5 * out6 */out3
                 +  /load* down * out6 * out3
                 +  /load*/down */out5 * out6
                 +  /load*/out4 * out5 * out6
                 +   load* data6;

 out7.ena        = enable;
 out7           :=  /load* down */out4 */out5 */out6 */out7 */out3 */out2 */out1 */out0 * cin
                 +  /load*/down * out4 * out5 * out6 */out7 * out3 * out2 * out1 * out0 * cin
                 +  /load* out7 */cin
                 +  /load*/out5 * out6 * out7
                 +  /load*/out6 * out7 * out0
                 +  /load* out5 * out7 */out0
                 +  /load*/out6 * out7 * out1
                 +   load* data7;

 out3.ena        = enable;
 out3           :=  /load* down */out3 */out2 */out1 */out0 * cin
                 +  /load*/down */out3 * out2 * out1 * out0 * cin
                 +  /load* out3 */cin
                 +  /load* down * out3 * out2
                 +  /load*/down * out3 */out0
                 +  /load* out3 */out1 * out0
                 +  /load* out3 */out2 * out1
                 +   load* data3;

 out2.ena        = enable;
 out2           :=  /load* down */out2 */out1 */out0 * cin
                 +  /load*/down */out2 * out1 * out0 * cin
                 +  /load* out2 */cin
                 +  /load* out2 */out1 * out0
                 +  /load*/down * out2 */out0
                 +  /load* down * out2 * out1
                 +   load* data2;

 out1.ena        = enable;
 out1           :=  /load* down */out1 */out0 * cin
                 +  /load*/down */out1 * out0 * cin
                 +  /load* out1 */cin
                 +  /load*/down * out1 */out0
                 +  /load* down * out1 * out0
                 +   load* data1;

 out0.ena        = enable;
 out0           :=  /load*/out0 * cin
                 +  /load* out0 */cin
                 +   load* data0;




vector CHH0HHNHHHHHHHHHHHHHNHHHHHHH ' 1
vector CHH0HHNHHHHHHH0HHHHHNHHHHLHH ' 2
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 3
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 4
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 5
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 6
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 7
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 8
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 9
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 10
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 11
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 12
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 13
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 14
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 15
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 16
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 17
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 18
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 19
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 20
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 21
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 22
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 23
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 24
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 25
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 26
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 27
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 28
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 29
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 30
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 31
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 32
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 33
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 34
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 35
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 36
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 37
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 38
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 39
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 40
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 41
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 42
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 43
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 44
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 45
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 46
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 47
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 48
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 49
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 50
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 51
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 52
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 53
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 54
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 55
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 56
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 57
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 58
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 59
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 60
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 61
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 62
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 63
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 64
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 65
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 66
vector C0H0HHNHHHHHHH0HHLHLNHHHLHH0 ' 67
vector C0H0HHNHHHHHHH0HHLHLNHHLHLH0 ' 68
vector C0H0HHNHHHHHHH0HHLHLNHHLLHH0 ' 69
vector C0H0HHNHHHHHHH0HHLHLNHHHHLH0 ' 70

end