this is an 8 bit up/down counter equations were reduced by ISDATA LOG/iC Device 26v12 clock = 1 load = 2 data0 = 3 clock2 = 4 data1 = 5 data2 = 6 data3 = 8 data4 = 9 data5 = 10 data6 = 11 data7 = 12 down = 13 enable = 14 cout = 15 ' carry output cin = 16 ' carry in out4 = 17 out5 = 18 out6 = 19 out7 = 20 out3 = 22 out2 = 23 out1 = 24 out0 = 25 /sr0.if = 26 sr1.rf = 27 reset = 28 start areset = reset * /down; spreset = reset * down; /sr0.clk2 /:= out0 * /sr0 ' 26 + /out0 * sr0; sr1.clk2 = out0 * sr0 * /sr1 ' 27 + /out0 * sr1 + /sr0 * sr1; cout /= /load* down */out4 */out5 */out6 */out7 */out3 */out2 */out1 */out0 * cin + /load*/down * out4 * out5 * out6 * out7 * out3 * out2 * out1 * out0 * cin ; out4.ena = enable; out4 := /load* down */out4 */out3 */out2 */out1 */out0 * cin + /load*/down */out4 * out3 * out2 * out1 * out0 * cin + /load* out4 */cin + /load* down * out4 * out3 + /load*/down * out4 */out0 + /load* out4 */out1 * out0 + /load* out4 */out3 * out2 + /load* out4 */out2 * out1 + load* data4; out5.ena = enable; out5 := /load* down */out4 */out5 */out3 */out2 */out1 */out0 * cin + /load*/down * out4 */out5 * out3 * out2 * out1 * out0 * cin + /load* out5 */cin + /load* out4 * out5 */out1 + /load*/out4 * out5 * out3 + /load* down * out5 * out1 + /load*/down * out5 */out0 + /load* out5 */out2 * out0 + /load* out5 */out3 * out2 + load* data5; out6.ena = enable; out6 := /load* down */out4 */out5 */out6 */out3 */out2 */out1 */out0 * cin + /load*/down * out4 * out5 */out6 * out3 * out2 * out1 * out0 * cin + /load* out6 */cin + /load* out5 * out6 */out3 + /load* down * out6 * out3 + /load*/down */out5 * out6 + /load*/out4 * out5 * out6 + /load* out4 * out6 */out0 + /load*/out5 * out6 * out0 + /load*/out5 * out6 * out1 + /load* out6 * out2 */out1 + /load*/down * out6 */out2 + load* data6; out7.ena = enable; out7 := /load* down */out4 */out5 */out6 */out7 */out3 */out2 */out1 */out0 * cin + /load*/down * out4 * out5 * out6 */out7 * out3 * out2 * out1 * out0 * cin + /load* out7 */cin + /load*/out5 * out6 * out7 + /load*/out6 * out7 * out0 + /load* out5 * out7 */out0 + /load*/out6 * out7 * out1 + /load*/down * out7 */out1 + /load* down * out5 * out7 + /load*/out6 * out7 * out2 + /load*/down * out7 */out2 + /load*/out6 * out7 * out3 + /load* out4 * out7 */out3 + /load*/down */out4 * out7 + load* data7; out3.ena = enable; out3 := /load* down */out3 */out2 */out1 */out0 * cin + /load*/down */out3 * out2 * out1 * out0 * cin + /load* out3 */cin + /load* down * out3 * out2 + /load*/down * out3 */out0 + /load* out3 */out1 * out0 + /load* out3 */out2 * out1 + load* data3; out2.ena = enable; out2 := /load* down */out2 */out1 */out0 * cin + /load*/down */out2 * out1 * out0 * cin + /load* out2 */cin + /load* out2 */out1 * out0 + /load*/down * out2 */out0 + /load* down * out2 * out1 + load* data2; out1.ena = enable; out1 := /load* down */out1 */out0 * cin + /load*/down */out1 * out0 * cin + /load* out1 */cin + /load*/down * out1 */out0 + /load* down * out1 * out0 + load* data1; out0.ena = enable; out0 := /load*/out0 * cin + /load* out0 */cin + load* data0; vector CHHCHHNHHHHHHHHHHHHHLHHHHLLH vector CHHCHHNHHHHH0HHHLLLLLLLLLHLH vector C0HCHHNHHHHH0HHHLLLLLLLLHHL0 vector C0HCHHNHHHHH0HHHLLLLLLLHLLL0 vector C0HCHHNHHHHH0HHHLLLLLLLHHLH0 vector C0HCHHNHHHHH0HHHLLLLLLHLLHH0 vector C0HCHHNHHHHH0HHHLLLLNLHLHHH0 vector C0HCHHNHHHHH0HHHLLLLNLHHLLH0 vector C0HCHHNHHHHH0HHHLLLLNLHHHLL0 vector C0HCHHNHHHHH0HHHLLLLNHLLLHL0 vector C0HCHHNHHHHH0HHHLLLLNHLLHHL0 vector C0HCHHNHHHHH0HHHLLLLNHLHLLL0 vector C0HCHHNHHHHH0HHHLLLLNHLHHLH0 vector C0HCHHNHHHHH0HHHLLLLNHHLLHH0 vector C0HCHHNHHHHH0HHHLLLLNHHLHHH0 vector C0HCHHNHHHHH0HHHLLLLNHHHLLH0 vector C0HCHHNHHHHH0HHHLLLLNHHHHLL0 vector C0HCHHNHHHHH0HHHHLLLNLLLLHL0 vector C0HCHHNHHHHH0HHHHLLLNLLLHHL0 vector C0HCHHNHHHHH0HHHHLLLNLLHLLL0 vector C0HCHHNHHHHH0HHHHLLLNLLHHLH0 vector C0HCHHNHHHHH0HHHHLLLNLHLLHH0 vector C0HCHHNHHHHH0HHHHLLLNLHLHHH0 vector C0HCHHNHHHHH0HHHHLLLNLHHLLH0 vector C0HCHHNHHHHH0HHHHLLLNLHHHLL0 vector C0HCHHNHHHHH0HHHHLLLNHLLLHL0 vector C0HCHHNHHHHH0HHHHLLLNHLLHHL0 vector C0HCHHNHHHHH0HHHHLLLNHLHLLL0 vector C0HCHHNHHHHH0HHHHLLLNHLHHLH0 vector C0HCHHNHHHHH0HHHHLLLNHHLLHH0 vector C0HCHHNHHHHH0HHHHLLLNHHLHHH0 vector C0HCHHNHHHHH0HHHHLLLNHHHLLH0 vector C0HCHHNHHHHH0HHHHLLLNHHHHLL0 vector C0HCHHNHHHHH0HHHLHLLNLLLLHL0 vector C0HCHHNHHHHH0HHHLHLLNLLLHHL0 vector C0HCHHNHHHHH0HHHLHLLNLLHLLL0 vector C0HCHHNHHHHH0HHHLHLLNLLHHLH0 vector C0HCHHNHHHHH0HHHLHLLNLHLLHH0 vector C0HCHHNHHHHH0HHHLHLLNLHLHHH0 vector C0HCHHNHHHHH0HHHLHLLNLHHLLH0 vector C0HCHHNHHHHH0HHHLHLLNLHHHLL0 vector C0HCHHNHHHHH0HHHLHLLNHLLLHL0 vector C0HCHHNHHHHH0HHHLHLLNHLLHHL0 vector C0HCHHNHHHHH0HHHLHLLNHLHLLL0 vector C0HCHHNHHHHH0HHHLHLLNHLHHLH0 vector C0HCHHNHHHHH0HHHLHLLNHHLLHH0 vector C0HCHHNHHHHH0HHHLHLLNHHLHHH0 vector C0HCHHNHHHHH0HHHLHLLNHHHLLH0 vector C0HCHHNHHHHH0HHHLHLLNHHHHLL0 vector C0HCHHNHHHHH0HHHHHLLNLLLLHL0 vector C0HCHHNHHHHH0HHHHHLLNLLLHHL0 vector C0HCHHNHHHHH0HHHHHLLNLLHLLL0 vector C0HCHHNHHHHH0HHHHHLLNLLHHLH0 vector C0HCHHNHHHHH0HHHHHLLNLHLLHH0 vector C0HCHHNHHHHH0HHHHHLLNLHLHHH0 vector C0HCHHNHHHHH0HHHHHLLNLHHLLH0 vector C0HCHHNHHHHH0HHHHHLLNLHHHLL0 vector C0HCHHNHHHHH0HHHHHLLNHLLLHL0 vector C0HCHHNHHHHH0HHHHHLLNHLLHHL0 vector C0HCHHNHHHHH0HHHHHLLNHLHLLL0 vector C0HCHHNHHHHH0HHHHHLLNHLHHLH0 vector C0HCHHNHHHHH0HHHHHLLNHHLLHH0 vector C0HCHHNHHHHH0HHHHHLLNHHLHHH0 vector C0HCHHNHHHHH0HHHHHLLNHHHLLH0 vector C0HCHHNHHHHH0HHHHHLLNHHHHLL0 vector C0HCHHNHHHHH0HHHLLHLNLLLLHL0 vector C0HCHHNHHHHH0HHHLLHLNLLLHHL0 vector C0HCHHNHHHHH0HHHLLHLNLLHLLL0 vector C0HCHHNHHHHH0HHHLLHLNLLHHLH0 vector C0HCHHNHHHHH0HHHLLHLNLHLLHH0 end