this is an 8 bit up/down counter
equations were reduced by ISDATA LOG/iC


Device 6001

 clock          = 13
 load           = 2
 data0          = 3
 data1          = 4
 data2          = 5
 data3          = 6
 data4          = 7
 data5          = 8
 data6          = 9
 data7          = 10
 down           = 11
 enable         = 1
 cout           = 14    ' carry output
 out4           = 15
/out5           = 16    ' one inverted output
 out6           = 17
 out7           = 18
 out3           = 19
 out2           = 20
 out1           = 21
 out0           = 22
 Q0             = 23
 cin	 	= 49         ' carry in  - default condition

 hreg22         = 32         ' use these to reference Q1 in the
 hreg23         = 33         ' macrocells
 hreg16         = 34         ' this register is hidden
 hreg17         = 35
 hreg18         = 36
 hreg19         = 37
 hreg20         = 38
 hreg21         = 39

' use these nodes for alternate feedback form either Q0 or the physical pin
' If not registered, then the node is Q0
' If     registered, then the node is the physical pin

' label           node       ' input term function

start

 cout           /=  /load* down */out4 */out5 */out6 */out7 */out3 */out2 */hreg21 */hreg22 * cin
                 +  /load*/down * out4 * out5 * out6 * out7 * out3 * out2 * hreg21 * hreg22 * cin  ;

 out4.ena      = /enable;
 out4           :=  /load* down */out4 */out3 */out2 */hreg21 */hreg22 * cin
                 +  /load*/down */out4 * out3 * out2 * hreg21 * hreg22 * cin
                 +  /load* out4 */cin
                 +  /load* down * out4 * out3
                 +  /load*/down * out4 */hreg22
                 +  /load* out4 */hreg21 * hreg22
                 +  /load* out4 */out3 * out2
                 +  /load* out4 */out2 * hreg21
                 +   load* data4;

/out5.ena      = /enable;
/out5          /:=  /load* down */out4 */out5 */out3 */out2 */hreg21 */hreg22 * cin
                 +  /load*/down * out4 */out5 * out3 * out2 * hreg21 * hreg22 * cin
                 +  /load* out5 */cin
                 +  /load* out4 * out5 */hreg21
                 +  /load*/out4 * out5 * out3
                 +  /load* down * out5 * hreg21
                 +  /load*/down * out5 */hreg22
                 +  /load* out5 */out2 * hreg22
                 +  /load* out5 */out3 * out2
                 +   load* data5;

 out6.ena      = /enable;
 out6           :=  /load* down */out4 */out5 */out6 */out3 */out2 */hreg21 */hreg22 * cin
                 +  /load*/down * out4 * out5 */out6 * out3 * out2 * hreg21 * hreg22 * cin
                 +  /load* out6 */cin
                 +  /load* out5 * out6 */out3
                 +  /load* down * out6 * out3
                 +  /load*/down */out5 * out6
                 +  /load*/out4 * out5 * out6
                 +  /load* out4 * out6 */hreg22
                 +  /load*/out5 * out6 * hreg22
                 +  /load*/out5 * out6 * hreg21
                 +  /load* out6 * out2 */hreg21
                 +  /load*/down * out6 */out2
                 +   load* data6;

 out7.ena      = /enable;
 out7            =  out6;

 out3.ena      = /enable;
 out3           :=  /load* down */out3 */out2 */hreg21 */hreg22 * cin
                 +  /load*/down */out3 * out2 * hreg21 * hreg22 * cin
                 +  /load* out3 */cin
                 +  /load* down * out3 * out2
                 +  /load*/down * out3 */hreg22
                 +  /load* out3 */hreg21 * hreg22
                 +  /load* out3 */out2 * hreg21
                 +   load* data3;

 out2.ena      = /enable;
 out2           :=  /load* down */out2 */hreg21 */hreg22 * cin
                 +  /load*/down */out2 * hreg21 * hreg22 * cin
                 +  /load* out2 */cin
                 +  /load* out2 */hreg21 * hreg22
                 +  /load*/down * out2 */hreg22
                 +  /load* down * out2 * hreg21
                 +   load* data2;

 out1.ena        = /enable;
 out1            =  hreg21;

 hreg21         :=  /load* down */hreg21 */hreg22 * cin
                 +  /load*/down */hreg21 * hreg22 * cin
                 +  /load* hreg21 */cin
                 +  /load*/down * hreg21 */hreg22
                 +  /load* down * hreg21 * hreg22
                 +   load* data1;

 out0.ena        = /enable;
 out0            = hreg22;

 hreg22         :=  /load*/hreg22 * cin
                 +  /load* hreg22 */cin
                 +   load* data0;

 Q0.ena          =  0;         ' this demonstrates the hidden use of Q0
 Q0	         = /Q0;        ' this toggles Q0 without using the pin

'
'pin23.ena	 =  0;         [ comment ]
'pin23          := /pin23;       this also would work, but
'				 the input cin would have to be node 51

vector 01000000000NCHLHLLLLLL0N ' 1      test vectors made by PAL 'G' command
vector 00000000001NCHHLHHHHHH1N ' 2
vector 00000000001NCHHLHHHHHL1N ' 3
vector 00000000001NCHHLHHHHLH1N ' 4
vector 00000000001NCHHLHHHHLL1N ' 5
vector 00000000001NCHHLHHHLHH1N ' 6
vector 00000000001NCHHLHHHLHL1N ' 7
vector 00000000001NCHHLHHHLLH1N ' 8
vector 00000000001NCHHLHHHLLL1N ' 9
vector 00000000001NCHHLHHLHHH1N ' 10
vector 00000000001NCHHLHHLHHL1N ' 11
vector 00000000001NCHHLHHLHLH1N ' 12
vector 00000000001NCHHLHHLHLL1N ' 13
vector 00000000001NCHHLHHLLHH1N ' 14
vector 00000000001NCHHLHHLLHL1N ' 15
vector 00000000001NCHHLHHLLLH1N ' 16
vector 00000000001NCHHLHHLLLL1N ' 17
vector 00000000001NCHHLHHLLLL0N ' 18
vector 00000000001NCHHLHHLLLL0N ' 19
vector 00000000000NCHHLHHLLLH1N ' 20
vector 00000000000NCHHLHHLLHL1N ' 21
vector 00000000000NCHHLHHLLHH1N ' 22
vector 00000000000NCHHLHHLHLL1N ' 23
vector 00000000000NCHHLHHLHLH1N ' 24
vector 00000000000NCHHLHHLHHL1N ' 25
vector 00000000000NCHHLHHLHHH1N ' 26
vector 00000000000NCHHLHHHLLL1N ' 27
vector 00000000000NCHHLHHHLLH1N ' 28
vector 00000000000NCHHLHHHLHL1N ' 29
vector 00000000000NCHHLHHHLHH1N ' 30
vector 00000000000NCHHLHHHHLL1N ' 31
vector 00000000000NCHHLHHHHLH1N ' 32
vector 00000000000NCHHLHHHHHL1N ' 33
vector 00000000000NCLHLHHHHHH1N ' 34
vector 00000000000NCHLHLLLLLL1N ' 35
vector 00000000000NCHLHLLLLLH1N ' 36
vector 00000000001NCLLHLLLLLL1N ' 37
vector 00000000001NCHHLHHHHHH1N ' 38
vector 00000000001NCHHLHHHHHL1N ' 39
vector 00000000001NCHHLHHHHLH1N ' 40
vector 00000000001NCHHLHHHHLL1N ' 41

end