this is an 8 bit up/down counter equations were reduced by ISDATA LOG/iC Device 22v10 clock = 1 load = 2 data0 = 3 data1 = 4 data2 = 5 data3 = 6 data4 = 7 data5 = 8 data6 = 9 data7 = 10 down = 11 enable = 13 cout = 14 ' carry output out4 = 15 out5 = 16 out6 = 17 out7 = 18 out3 = 19 out2 = 20 out1 = 21 out0 = 22 cin = 23 ' carry in start cout /= /load* down */out4 */out5 */out6 */out7 */out3 */out2 */out1 */out0 * cin + /load*/down * out4 * out5 * out6 * out7 * out3 * out2 * out1 * out0 * cin ; out4.ena = enable; out4 := /load* down */out4 */out3 */out2 */out1 */out0 * cin + /load*/down */out4 * out3 * out2 * out1 * out0 * cin + /load* out4 */cin + /load* down * out4 * out3 + /load*/down * out4 */out0 + /load* out4 */out1 * out0 + /load* out4 */out3 * out2 + /load* out4 */out2 * out1 + load* data4; out5.ena = enable; out5 := /load* down */out4 */out5 */out3 */out2 */out1 */out0 * cin + /load*/down * out4 */out5 * out3 * out2 * out1 * out0 * cin + /load* out5 */cin + /load* out4 * out5 */out1 + /load*/out4 * out5 * out3 + /load* down * out5 * out1 + /load*/down * out5 */out0 + /load* out5 */out2 * out0 + /load* out5 */out3 * out2 + load* data5; out6.ena = enable; out6 := /load* down */out4 */out5 */out6 */out3 */out2 */out1 */out0 * cin + /load*/down * out4 * out5 */out6 * out3 * out2 * out1 * out0 * cin + /load* out6 */cin + /load* out5 * out6 */out3 + /load* down * out6 * out3 + /load*/down */out5 * out6 + /load*/out4 * out5 * out6 + /load* out4 * out6 */out0 + /load*/out5 * out6 * out0 + /load*/out5 * out6 * out1 + /load* out6 * out2 */out1 + /load*/down * out6 */out2 + load* data6; out7.ena = enable; out7 := /load* down */out4 */out5 */out6 */out7 */out3 */out2 */out1 */out0 * cin + /load*/down * out4 * out5 * out6 */out7 * out3 * out2 * out1 * out0 * cin + /load* out7 */cin + /load*/out5 * out6 * out7 + /load*/out6 * out7 * out0 + /load* out5 * out7 */out0 + /load*/out6 * out7 * out1 + /load*/down * out7 */out1 + /load* down * out5 * out7 + /load*/out6 * out7 * out2 + /load*/down * out7 */out2 + /load*/out6 * out7 * out3 + /load* out4 * out7 */out3 + /load*/down */out4 * out7 + load* data7; out3.ena = enable; out3 := /load* down */out3 */out2 */out1 */out0 * cin + /load*/down */out3 * out2 * out1 * out0 * cin + /load* out3 */cin + /load* down * out3 * out2 + /load*/down * out3 */out0 + /load* out3 */out1 * out0 + /load* out3 */out2 * out1 + load* data3; out2.ena = enable; out2 := /load* down */out2 */out1 */out0 * cin + /load*/down */out2 * out1 * out0 * cin + /load* out2 */cin + /load* out2 */out1 * out0 + /load*/down * out2 */out0 + /load* down * out2 * out1 + load* data2; out1.ena = enable; out1 := /load* down */out1 */out0 * cin + /load*/down */out1 * out0 * cin + /load* out1 */cin + /load*/down * out1 */out0 + /load* down * out1 * out0 + load* data1; out0.ena = enable; out0 := /load*/out0 * cin + /load* out0 */cin + load* data0; vector C1000000000N1HLLLLLLLL0N ' 1 test vectors made by PAL 'G' command vector C0000000001N1HHHHHHHHH1N ' 2 vector C0000000001N1HHHHHHHHL1N ' 3 vector C0000000001N1HHHHHHHLH1N ' 4 vector C0000000001N1HHHHHHHLL1N ' 5 vector C0000000001N1HHHHHHLHH1N ' 6 vector C0000000001N1HHHHHHLHL1N ' 7 vector C0000000001N1HHHHHHLLH1N ' 8 vector C0000000001N1HHHHHHLLL1N ' 9 vector C0000000001N1HHHHHLHHH1N ' 10 vector C0000000001N1HHHHHLHHL1N ' 11 vector C0000000001N1HHHHHLHLH1N ' 12 vector C0000000001N1HHHHHLHLL1N ' 13 vector C0000000001N1HHHHHLLHH1N ' 14 vector C0000000001N1HHHHHLLHL1N ' 15 vector C0000000001N1HHHHHLLLH1N ' 16 vector C0000000001N1HHHHHLLLL1N ' 17 vector C0000000001N1HHHHHLLLL0N ' 18 vector C0000000001N1HHHHHLLLL0N ' 19 vector C0000000000N1HHHHHLLLH1N ' 20 vector C0000000000N1HHHHHLLHL1N ' 21 vector C0000000000N1HHHHHLLHH1N ' 22 vector C0000000000N1HHHHHLHLL1N ' 23 vector C0000000000N1HHHHHLHLH1N ' 24 vector C0000000000N1HHHHHLHHL1N ' 25 vector C0000000000N1HHHHHLHHH1N ' 26 vector C0000000000N1HHHHHHLLL1N ' 27 vector C0000000000N1HHHHHHLLH1N ' 28 vector C0000000000N1HHHHHHLHL1N ' 29 vector C0000000000N1HHHHHHLHH1N ' 30 vector C0000000000N1HHHHHHHLL1N ' 31 vector C0000000000N1HHHHHHHLH1N ' 32 vector C0000000000N1HHHHHHHHL1N ' 33 vector C0000000000N1LHHHHHHHH1N ' 34 vector C0000000000N1HLLLLLLLL1N ' 35 vector C0000000000N1HLLLLLLLH1N ' 36 vector C0000000001N1LLLLLLLLL1N ' 37 vector C0000000001N1HHHHHHHHH1N ' 38 vector C0000000001N1HHHHHHHHL1N ' 39 vector C0000000001N1HHHHHHHLH1N ' 40 vector C0000000001N1HHHHHHHLL1N ' 41 end