BUILDING A REPLACEMENT SMP MODULE. It is not hard to build a replacement SMP with 
all new components. Instead of the Intel 5C032, which most likely is no longer 
available, a PEEL (ICT) 18CV8 can be substituted. This module is sold by Jameco 
in the US and Farnell in France. EEPROM's type 93C46 are readily available from 
a number of vendors. Figure <a href="smpkey.pdf">smpkey.pdf</a> shows how these 
modules are interconnected and connected to socket IB8 when the key is plugged 
onto the motherboard. A small decoupling capacitor is wired between VCC and GND 
of the EEPROM. The 10k resistor may have helped solve a 5C032/EEPROM hazard in 
the original key, but may not be necessary with the 18CV8. It does not hurt however 
to leave it in place. Both the 18CV8 and 93C46 can be programmed on a sprint expert 
programmer. The 18CV8 does not even need any PAL in IB7 or IB8 to do so. The pld 
equations are listed in: <smp8.eqn><a href="SMP8.PLD">SMP8.PLD</a>, the JED file 
is <a href="SMP8.JED">SMP8.JED</a><smp8.jed>. For those of you who wonder how 
the 18CV8-based SMP key functions, the following description might be of interest: 
The PAL is the vehicle that interfaces the data bus on the sprint express motherboard 
with the EEPROM. Write commands from the sprint software direct the PAL to shift 
data stored in the EEPROM to a register on the PAL and drive it onto the data 
bus, where a software read command can pick it up. All data is handled serially 
bit-by-bit. Datasheets from 93C46 manufacturers such as <a href="93C46.pdf">at93c46.pdf</a> 
clearly describe the process and control signals involved: DI, DO, SK and CS. 
A read operation is started by command hex 38 on the data bus. The PAL uses it 
to activate register 'chip select' (CS) for the duration of a read operation. 
The EEPROM requires a 'read command' to be clocked in first. This is done with 
a start bit on the DI input, followed by 'one-zero' and a 6-bit address. The EEPROM 
is wired (ORG connected to VCC) to send back 16-bit serial data (2 bytes) after 
receiving the read command and address. It will clock out on its DO output a dummy 
0 bit, followed by the 16 data bits. SK is the clock used for all data transfers. 
The PAL generates SK pulses and DI information from software write commands following 
command 38. When all 16 data bits have been received on DO, registered, driven 
onto the data bus and read by the sprint software, the CS register is deactivated 
by the command hex 05. It is up to the sprint software to read as many double-bytes 
it wishes to read, at whatever addresses and for whatever purposes. The PAL will 
also enable write operations to the EEPROM whenever required. Combinatorial outputs 
on the PAL are used to provide power to the EEPROM (VCC and GND). These outputs 
are always enabled. Registers latch signals DI, DO, SK and CS when the PAL is 
clocked. Outputs DI, SK, and CS going to the EEPROM must also always be enabled. 
However the output of register DO should only be put on the sprint card data bus 
when the PAL input OE is active (down). Socket pins 18, 15, and 12 are available 
and have been programmed to receive DO signals. The sprint software looks specifically 
at pin 18. To minimize activity on register outputs DI, SK and DO, the equations 
for these registers require the CS register to be active, which means only during 
actual EEPROM read/write operations. The Intel 5C32 and PEEL 18V8 belong to the 
few modules where output enables can be individually programmed. Many 20-pin PAL's 
have one OE input common to all outputs and can therefore not be used. It may 
also be mentioned here that, since inputs OE are common to both sockets IB7 and 
IB8, one should never run modules in both sockets simultaneously. Doing so would 
have their outputs fight each other, possibly overheating and damaging a module.