From - Sun Nov 26 10:41:40 2000 Path: magic.fr!dt-cegetel!esplanade3000.net!fr.clara.net!bigger.fr.clara.net!cleanfeed.casema.net!newsfeed.wirehub.nl!newsfeed.germany.net!nntp-relay.ihug.net!ihug.co.nz!news.tig.com.au!not-for-mail From: Peter Jakacki Newsgroups: comp.arch.embedded Subject: Re: I2C routines for 68HC05? Date: Tue, 21 Nov 2000 11:52:50 +1000 Organization: Cybertronics Lines: 152 Message-ID: <3A19D572.73D0CF02@ihug.com.au> References: NNTP-Posting-Host: p402-tnt1.brs.ihug.com.au Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: bugstomper.ihug.com.au 974771574 22441 203.173.189.148 (21 Nov 2000 01:52:54 GMT) X-Mailer: Mozilla 4.72 [en] (Win98; I) X-Accept-Language: en,zh-TW Xref: magic.fr comp.arch.embedded:67131 X-mol: Magic OnLine V.DED-02012000 I2C routines for 6805?, sounds familiar, so I dug through some really old stuff I did and found some. This assumes a single master (as practically all I2C systems are) and includes the primitives necessary for EEPROM access. The general scheme to access serial EEPROM is this; TO READ: START PUT chip address PUT 1 or 2 byte address for memory location START ( PUT chip address with bit 0 set (read) GET data (repeat as necessary) STOP TO WRITE: START PUT chip address PUT 1 or 2 byte address for memory location PUT data (repeat as required up to page size) STOP (write cycle commences) If you need more help just drop me an email or icq on 70749123. Peter ;----------------------------- begin ----------------------------- ; ****************** IIC BUS DRIVERS *********** ;****** RAM ******** iicdat: res 1 iicflg: res 1 Scl EQU 7 Sda EQU 6 ;******* CODE ****** IICPUT: ; ; Send the byte over the IIC line ; STA iicdat ;hold data BCLR Scl,PB ;clock low BSET Scl,DDRB LDX #08 IPLP: ROL iicdat BCLR Scl,PB BCC IP0 BCLR Sda,DDRB BRA IPX IP0: BCLR Sda,PB BSET Sda,DDRB IPX: BSET Scl,PB DECX BNE IPLP BCLR Scl,PB BCLR Sda,DDRB BCLR 0,iicflg NOP NOP NOP NOP BSET Scl,PB BRCLR Sda,PB,NOACK BSET 0,iicflg NOACK BCLR Scl,PB RTS IICGET: BSET Scl,DDRB BCLR Scl,PB BCLR Sda,DDRB LDA #0 STA iicdat LDX #08 IGLP: NOP NOP BSET Scl,PB CLC BRCLR Sda,PB,IGX SEC IGX: ROL iicdat BCLR Scl,PB DECX BNE IGLP BRCLR 1,iicflg,NAK ;WRACK ? BCLR Sda,PB BSET Sda,DDRB BRA IG2 NAK: BSET Sda,PB BCLR Sda,DDRB IG2: BSET Scl,PB ;Clock the ACK out NOP NOP NOP BCLR Scl,PB BCLR Sda,DDRB LDA iicdat RTS IICINIT: BSET Scl,PB BSET Scl,DDRB BCLR Sda,DDRB RTS IICSTOP: BCLR Sda,PB BSET Sda,DDRB BSET Scl,PB BCLR Sda,DDRB ;data low to high while clock high RTS IICSTART: BCLR Sda,DDRB BSET Scl,PB BSET Scl,DDRB BCLR Sda,PB BSET Sda,DDRB RTS ;----------------------------- end ----------------------------- Pete Barnes wrote: > > To save me re-inventing the wheel, does anyone have routines for I2C > interface to 68HC05? (specifically EEPROM) > Any help appreciated > (I can write them myself but I don't particularly want to!) > -- > Pete Barnes -- \\\|/// \\ ~ ~ // (/ @ @ /) /\/\/\/\/\/\/\/\/\/\oOOo-(_)-oOOo\/\/\/\/\/\/\/\/\/\/\/\/\/\ \/ Peter Jakacki \/ /\ Cybertronics /\ \/ 16 Isdell St., \/ /\ Algester, Brisbane, QLD 4115 /\ \/ Australia \/ /\ ph: 61 7 3273-1409 fax: 61 7 3272-2449 /\ \/ mailto: cyb@ihug.com.au \/ /\ /\ \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/