ARM Architectural Reference Manual ( Prentice Hall by Dave Jaggar) © July 1996 includes the following data sheets:
This is the authoritative reference guide to the ARM RISC architecture from 
  Advanced RISC Machines. Produced by the architects that are actively working 
  on the ARM specification, the book contains detailed information about all versions 
  of the ARM and Thumb instruction sets, the memory management and cache functions, 
  as well as optimized code examples.

The ARM architecture is the basis of the world's most widely available 32-bit microprocessor.
ARM Powered microprocessors are being routinely designed into a wider range of products than any other 32-bit processor.
This diversity of applicability is made possible by the ARM architecture, resulting in optimal system solutions
at the crossroads of high performance, low consumption, and low cost.
In november 1990, ARM was formed to develop and promote the ARM architecture.
With initial investment from :
- Apple Computer
- Acorn
- VLSI Technology, the world leading ASIC supplier
Initially ARM devices where made by VLSI Technology, but ARM's business model is to license microprocessor designs to
a broad range of semiconductor manufacturers.
To date, this licensing strategy has resulted in twelve companies manufacturing ARM-based designs:
- VLSI Technology
- Texas Instruments (TI)
- Samsung Corporation
- NEC Corporation
- GEC Plessey Semiconductors (GEC)
- Cirrus Logic
- Digital Equipment Corporation
- Symbios Logic
- Sharp Corporation
- Asahi Kasai Microsystems (AKM)
- European Silicon Structures (ES2)
- Lucky Goldstar Corporation

1/ Architecture Overview

2/ Programmer's Model

3/ The ARM Instruction Set

4/ ARM Code Sequences

5/ The 26-bit Architectures

6/ The Thumb Instruction Set

7/ System Architecture and System Control Coprocessor


table des matieres complète:

Table des matières

Using this Manual
1 Architecture Overview
1.1 Overview
1.2 Exceptions
1.3 ARM Instruction Set
1.4 Branch Instructions
1.5 Data-Processing Instructions
1.6 Load and Store Instructions
1.7 Coprocessor Instructions
2 Programmer's Model
2.1 Data Types
2.2 Processor Modes
2.3 Registers
2.4 Program Status Registers
2.5 Exceptions
3 The ARM Instruction Set
3.1 Using this Chapter
3.2 Instruction Set Overview
3.3 The Condition Field
3.4 Branch Instructions
3.5 Data Processing
3.6 Multiply Instructions
3.7 Status Register Access
3.8 Load and Store Instructions
3.9 Load and Store Word or Unsigned Byte
3.10 Load and Store Halfword and Load
Signed Byte Instructions
3.11 Load and Store Multiple Instructions
3.12 Semaphore Instructions
3.13 Coprocessor Instructions
3.14 Extending the Instruction Set
3.15 Alphabetical List of ARM Instructions
3.16 Data-processing Operands
3.17 Load and Store Word or Unsigned Byte
Addressing Modes
3.18 Load and Store Halfword or Load
Signed Byte Addressing Modes
3.19 Load and Store Multiple Addressing
3.20 Load and Store Multiple Addressing
Modes (Alternative names)
3.21 Load and Store Coprocessor Addressing
4 ARM Code Sequences
4.1 Arithmetic Instructions
4.2 Branch Instructions
4.3 Load and Store Instructions
4.4 Load and Store Multiple Instructions
4.5 Semaphore Instructions
4.6 Other Code Examples
5 The 26-bit Architectures
5.1 Introduction
5.2 Format of Register 15
5.3 Writing just the PSR in 26-bit architectures
5.4 26-bit PSR Update Instructions
5.5 Address Exceptions
5.6 Backwards Compatibility from 32-bit Architectures
6 The Thumb Instruction Set
6.1 Using this Chapter
6.2 Introduction to Thumb
6.3 Instruction Set Overview
6.4 Branch Instructions
6.5 Data-processing Instructions
6.6 Load and Store Register Instructions
6.7 Load and Store Multiple Instructions
6.8 Alphabetical List of Thumb Instructions
7 System Architecture and System Control
7.1 Introduction
7.2 CP15 Access
7.3 CP15 Architectures
7.4 ARMv4 System Control Coprocessor
7.5 ARMv3 System Control Coprocessor
7.6 Memory Management Unit (MMU) Architecture
7.7 Cache and Write Buffer Control
7.8 Access Permissions
7.9 Domains
7.10 Aborts
7.11 MMU Faults
7.12 External Aborts
7.13 System-level Issues
7.14 Semaphores Index



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