INTEL Programmable Logic Handbook 1988 contains the following data sheets:
http://www.bitsavers.org/components/intel/_dataBooks/1988_Intel_Microcomputer_Programmable_Logic_Handbook.pdf
Overview
Ordering Information
EPLDs Erasable Programmable Logic Devices
5C031 300 Gate CHMOS H-Series Erasable Programmable Logic Device (H-EPLD)
5C032 300 Gate CHMOS H-Series Erasable Programmable Logic Device (H-EPLD)
5C060 / 5C090 600- / 900- GATE CHMOS H-SERIES Erasable Programmable Logic Device (H-EPLD)
5C121 1200 Gate CHMOS H-Series Erasable Programmable Logic Device
5C180 1800- Gate Erasable Programmable Logic Device
5AC312 Erasable Programmable Logic Device
Implemating Cascaded Logic in the 5C121 Application Brief AB-8
5C121 As a Three And One Half Digit Display Driver Application Brief AB-9
Square Pegs in Round Holes - A Fitting Tutorial for the 5C121 Application Brief AB-10
16-Bit Binary Counter Implementation Using the 5C060 EPLD Application Brief AB-11
Designing a Mailbox Memory for Two 80C31 Microcontrollers Using EPLDs Application Brief AB-12
A typical Latch/Register Construction in EPLDs Application Brief AB-16
TTL Macro Library Listing for EPLD Designs Application Brief AB-18
Applying The 5C121 Architecture Application Note AP-271
The 5C060 Unification of a CHMOS System Application Note AP-272
Implementing a CMOS Bus Arbiter/Controller in the 5C060 EPLD Application Note AP-276
Simulation of EPLD Timing Application Note AP-304
EPLDs, PLAs and TTL Comparing the "Hidden Costs" in Production Application Note AP-307
Techniques for Modular EPLD Designs
Crosspoint Switch: A PLD Approach Application Report AR-450
A Programmable Logic Mailbox for 80C31 Microcontrollers Application Report AR-451
Regain lost I/O ports with erasable PLDs Application Report AR-454
Advanced Architecture EPLDs
5CBIC Programmable Bus Interface Controller
Dual-Port Memory Control Using The 5CBIC Application Note AP-305
The Multiplexed Bus Interface with the 5CBIC Application Note AP-308
DRAM Address Interface with the 5CBIC Application Note AP-309
Programmable logic shrinks bus-interface designs Application Report AR-453
Development Support Tools
iPLDS II The Intel Programmable Logic Development System Version II
iUP-PC Intel Universal Programmer for the personal Computer
SCHEMA II-PLD Schematic Capture Software
iPLS II Macro Librarian
Utilities
PAL2ADF Utility
JED2HEX Conversion Utility
Implementing an EPLD Design Using Intel's Programmable Logic Development System Application Note AP-279 Dice Rolling Project
Using Macros in EPLD Designs Application Note AP-311
Creating Macros for EPLD Designs Application Note AP-312
Tools for Optimizing PLD Designs
Appendix
Second-Source Cross Reference Intel vs Altera
back to index
http://www.bitsavers.org/components/intel/_dataBooks/1988_Intel_Microcomputer_Programmable_Logic_Handbook.pdf
Overview
Ordering Information
EPLDs Erasable Programmable Logic Devices
5C031 300 Gate CHMOS H-Series Erasable Programmable Logic Device (H-EPLD)
5C032 300 Gate CHMOS H-Series Erasable Programmable Logic Device (H-EPLD)
5C060 / 5C090 600- / 900- GATE CHMOS H-SERIES Erasable Programmable Logic Device (H-EPLD)
5C121 1200 Gate CHMOS H-Series Erasable Programmable Logic Device
5C180 1800- Gate Erasable Programmable Logic Device
5AC312 Erasable Programmable Logic Device
Implemating Cascaded Logic in the 5C121 Application Brief AB-8
5C121 As a Three And One Half Digit Display Driver Application Brief AB-9
Square Pegs in Round Holes - A Fitting Tutorial for the 5C121 Application Brief AB-10
16-Bit Binary Counter Implementation Using the 5C060 EPLD Application Brief AB-11
Designing a Mailbox Memory for Two 80C31 Microcontrollers Using EPLDs Application Brief AB-12
A typical Latch/Register Construction in EPLDs Application Brief AB-16
TTL Macro Library Listing for EPLD Designs Application Brief AB-18
Applying The 5C121 Architecture Application Note AP-271
The 5C060 Unification of a CHMOS System Application Note AP-272
Implementing a CMOS Bus Arbiter/Controller in the 5C060 EPLD Application Note AP-276
Simulation of EPLD Timing Application Note AP-304
EPLDs, PLAs and TTL Comparing the "Hidden Costs" in Production Application Note AP-307
Techniques for Modular EPLD Designs
Crosspoint Switch: A PLD Approach Application Report AR-450
A Programmable Logic Mailbox for 80C31 Microcontrollers Application Report AR-451
Regain lost I/O ports with erasable PLDs Application Report AR-454
Advanced Architecture EPLDs
5CBIC Programmable Bus Interface Controller
Dual-Port Memory Control Using The 5CBIC Application Note AP-305
The Multiplexed Bus Interface with the 5CBIC Application Note AP-308
DRAM Address Interface with the 5CBIC Application Note AP-309
Programmable logic shrinks bus-interface designs Application Report AR-453
Development Support Tools
iPLDS II The Intel Programmable Logic Development System Version II
iUP-PC Intel Universal Programmer for the personal Computer
SCHEMA II-PLD Schematic Capture Software
iPLS II Macro Librarian
Utilities
PAL2ADF Utility
JED2HEX Conversion Utility
Implementing an EPLD Design Using Intel's Programmable Logic Development System Application Note AP-279 Dice Rolling Project
Using Macros in EPLD Designs Application Note AP-311
Creating Macros for EPLD Designs Application Note AP-312
Tools for Optimizing PLD Designs
Appendix
Second-Source Cross Reference Intel vs Altera
back to index