The 8086 User's manual October 1979 INTEL Corporation (PDF-208 Pages -9.21Mb) (Chapter 1, 2 and 4)

http://bitsavers.org/components/intel/_dataBooks/1981_iAPX_86_88_Users_Manual.pdf (PDF File - 53.7 Mb) Interestingly enough, this 1981 edition of the 86/88 User's Manual has the same structure as the volume from 1979 (except for the title since Intel changed product names in the meanwhile)

1979 Intel The 8086 Family Users Manual 197910.pdf (PDF - 760 pages - 99.4Mb)

Chapter 1 Introduction

Manual Organization
8086 Family Architecture
Functional Distribution
- Microprocessors
- Interrupt Controller
- Bus Interface Components
Multiprocessing
Bus Organization
- Local Bus
- System Bus
- Processing Modules
- Bus Implementation Examples
Development Aids

Chapter 2 The 8086 and 8088 Central Processing Units

Processor Overview
Processor Architecture
- Execution Unit
- Bus Interface Unit
- General Registers
- Segment Register
- Instruction Pointer
- Flags
- 8080 /8085 Register and Flag Correspondance
- Mode Selection

Memory
-Storage Organization
- Segmentation
- Physical address Generation
- Dynamically Relocatable Code
- Stack Implementation
- Dedicated and Reserved Memory Locations
-8086/8088 Memory Access Differences

Input/Output
- Input/Output Space
- Restricted I/O Locations
- 8086/8088 Memory Access Differences
- Memory-Mapped I/O
- Direct Memory Access
- 8089 Input/Output Processor (IOP)

Multiprocessing Features
- Bus Lock
- WAIT and !TEST
- Escape
- Request / Grant Lines
- Multibus Architecture
-8289 Bus Arbiter

Processor Control and Monitoring
- Interrupts
* External interrupts
* Internal Interrupts
* Interrupt Pointer Table
* Interrupt Procedures
* Single-step (Trap) Interrupt
* Breakpoint Interrupt

- System Reset
-Instruction Queue Status
- Processor halt
-Status Lines

Instruction Set
- Data Transfer Instructions
* General Purpose Data Transfers
* Address Object Transfers
* Flag Transfers
- Arithmetic Instructions
* Arithmetic Data Formats
* Arithmetic Instructions and Flags
* Addition
* Substraction
* Multiplication
* Division

-Bit Manipulation Instructions
* Logical
* Shifts
* Rotates
-String instructions
- Program Transfer Instructions
* Unconditional Transfers
* Iteration Control
* Interrupts Instructions
- Processor Control Instructions
* Flag Operations
* External Synchronization
* No Operation
- Instruction Set Reference Information

Addressing Modes
- Register and Immediates Operands
- Memory Addressing Modes
* The Effective Address
* Direct Addressing
* Register Indirect Addressing
* Based Addressing
* Indexed Addressing
* Based Indexed Addressing
* String Addressing
- I/O Addressing

Programming Facilities
-Software Development Overview
-PL/M-86
* Statements and Comments
* Data Definition
* Assignment Statement
* Program Flow Statements
* Procedures
-ASM-86
* Statements
* Constants
* Defining Data
* Records
* Structures
* Addressing Modes
* Segment Controls
* Procedures

LINK-86
LOC-86
LIB-86
OH-86
CONV-86
Sample Programs

Programming Guidelines and Examples
- Programming Guidelines
* Segments and Segment Registers
* Self Modifying Code
* Input/output
* Operating Systems
* Interrupt Service Procedures
* Stack-Based Parameters
* Flag Images
- Programming Examples
* Procedures
* Jump and Calls
* Records
* Dynamic Code Relocation
* Memory-Mapped I/O
* Breakpoints
* Interrupt Procedures
* String Operations

Chapter 3 The 8089 INPUT/OUTPUT PROCESSOR

Processor Overview
- Evolution
- Principles of Operation
* CPU/IOP Communications
* Channels
* Channel Programs (Task Blocks)
* DMA Transfers
* Bus Configurations
* A Sample Transaction
- Applications

Processor Architecture
- Common Contro Unit (CCU)
- Arithmetic / Logic Unit (ALU)
- Assembly / Disassembly Registers
- Instruction Fetch Unit
- Bus Interface Unit (BIU)
Channels
* I/O Control
* Registers
* Program Status Word
* Tag Bits
* Concurrent Channel Operation

Memory
- Storage Organization
- Dedicated and Reserved Memory Locations
- Dynamic Relacation
- Memory Access

Input /Output
- Programmed I/O
* I/O Instructions
* Device Addressing
* I/O Bus Transfers
- DMA Transfers
* Preparing the Device Controller
* Preparing the channel
* Beginning the Transfer
* DMA Transfer Cycle
* Following the Transfer

Multiprocessing Features
- Bus Arbitration
* Request / Grant Line
* 8289 BusArbiter
* Bus Arbitration for IOP Configurations
- Bus Load Limit
- Bus Lock

Processor Control and Monitoring
- Initialization
-Channel Commands
-DRQ (DMA Request)
-EXT (External Terminate)
-Interrupt
- Status Lines

Instruction Set
- Data transfer Instructions
- Arithmetic Instructions
- Logical and Bit Manipulation Instructions
- Program Transfer Instructions
- Processor Control Instructions
- Instruction Set Reference Information

Addressing Modes
- Register and Immediate Operands
-Memory addressing Modes
* The Effective Address
* Based Addressing
* Offset Addressing
* Indexed Addressing
* Index Auto-Increment Addressing

Programming Facilities
ASM-89
- Statements
- Constants
- Defining Data
- Structures
- Addressing Modes
- Program Transfer Targets
- Procedures
- Segment Control
- Intermodule Communication
- Sample Program
- Linking and locating ASM-89 Modules

Programming Guidelines and Examples
- Programming Guidelines
- Segments
-Self-Modifying Code
- I/O System Design
-Programming Examples
Initialization and Dispatch
Memory-to-Memory Transfer
Saving and Restoring Registers

Chapter 4 Hardware Reference Information
Introduction
8086 and 8088 CPUs
- CPU Architecture
- Bus Operation
- Clock Circuit
- Minimum / Maximum Mode
* Minimum Mode
* Maximum Mode
- External Memory Addressing
- I/O Interfacing
- Interrupts
- Machine Instruction Encoding and Decoding
8086 Instruction Sequence

8089 I/O Processor
-System Configuration
* Local Mode
* Remote Mode
- Bus Operation
- Initialization
- I/O Dispatching
- DMA Transfers
- DMA Termination
-Peripheral Interfacing
- Instruction Encoding

APPENDIX A Application Notes
AP-87 8086 System Designs
AP-61 Multitasking for the 8086
AP-50 Debugging Strategic and Considerations for 8089 Systems
AP-51 Designing 8086, 8088, 8089 Multiprocessing Systems with the 8089 Bus Arbiter
AP-59 Using the 8259 Programmable Interrupt Controller
AP-28A Intel Multibus Interfacing
AP-43 Using the iSBC-957 Execution Vehicule 8086 Program Code

APPENDIX B DEVICE SPECIFICATIONS
8086 Family
8086 /8086-2 / 8086-4 16-Bit HMOS Microprocessor
M8086 16-Bit HMOS Microprocessor
I8086 16-Bit HMOS Microprocessor
8088 8 -Bit HMOS Microprocessor
8089 8/ 16-Bit HMOS I/O Processor
8282/ 8283 Octal Latch
8284 Clock Generator and Driver for 8086, 8088, 8089 Processors
M8284 Clock Generator and Driver for 8086, 8088, 8089 Processors
I 8284 Clock Generator and Driver for 8086, 8088, 8089 Processors
8286/ 8287 Octal Bus Transceiver
8288 Bus Controller for 8086, 8088, 8089 Processors
8289 Bus Arbitrer
8237 / 8237-2 High Performance Programmable DMA Controller
8259A/ 8259A-2 / 8289A-8 Programmable Interrupt Controller

8085 Peripherals

8155/ 8156 / 8155-2 / 8156-2 2048 Bit Static MOS RAM with I/O Ports and Timer
8185 / 8185-2 1024* 8-Bit Static RAM for MCS-85
8355 / 8355-2 384-Bit ROM with I/O
8755A / 8755A-2 16384-Bit EPROM With I/O

Standard Peripherals

8041 /8741 Universal Peripheral Interfa 8-Bit Microcomputer
8202 Dynamic RAM Controller
8205 High Speed 1 Out 8 Binary Decoder
8251A Programmable Communication interface
8253 / 8253-5 Programmable Interval Timer
8255A / 8255A-5 Programmable Peripheral Interface
8271 / 8271-6 / 8271-8 Programmable Floppy Disk Controller
8273 Programmable HDLC / SDLC Protocol Controller
8275 Programmable CRT Controller
8279 /8279-5 Programmable Keyboard / Display Interface
8291 GPIB Talker / Listener
8292 GPIB Controller
8293 GPIB Transveiver
8294 Data Encryption Unit
8295 Dot Matrix Printer Controller

RAM Memories

2114A 1024x4Bit Static RAM
2142 1024x4 Bit Static RAM
2148 1024x4 Bit Static RAM

EPROM Memories
2716 16K (2Kx8) UV Erasable PROM
2732 32K (4k x8 bits) UV Erasable PROM
2758 8K (1Kx8) UV Erasable Low Power PROM

Development Tools
Model 230 Intellec Series II Microcomputer Development System
8086/ 8088 Software Development Package
8089 Assembler Support Package
ICE-86 8086 In Circuit Emulator
iSBC 86/12A Interface and Execution Package
iSBC 300/340 isBC 300 32KByte RAM
-Expansion Module iSBC 300 16K-Byte
- EPROM / ROM Expansion Module
SDK-86 MCS-86 System Design Kit
SDK-C86, MCS-86 System Design Kit

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15 août, 2021